CUDA: size routed MoE MMQ N-tiles from typical expert width on RDNA3

ggml/src/ggml-cuda/mmq.cuh

@@ -1466,12 +1466,32 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a
          ntx_fd);
 }
 
+static bool mmq_use_routed_moe_ncols_picker(const int cc) {
+    return (GGML_CUDA_CC_IS_NVIDIA(cc) && cc >= GGML_CUDA_CC_VOLTA) ||
+           GGML_CUDA_CC_IS_CDNA(cc) ||
+           GGML_CUDA_CC_IS_RDNA2(cc) ||
+           GGML_CUDA_CC_IS_RDNA3(cc) ||
+           GGML_CUDA_CC_IS_RDNA4(cc);
+}
+
 template <ggml_type type, bool fallback>
 void mul_mat_q_switch_J(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) {
     const int    id    = ggml_cuda_get_device();
     const int    cc    = ggml_cuda_info().devices[id].cc;
     const size_t smpbo = ggml_cuda_info().devices[id].smpbo;
 
+    int64_t ncols_picker = args.ncols_max;
+    if (args.expert_bounds != nullptr && mmq_use_routed_moe_ncols_picker(cc) && args.nchannels_x > 0) {
+        // In routed MoE, ncols_max is the worst-case per-expert width. Size the
+        // MMQ N-tile from the typical routed width while it is below the current
+        // architecture's max tile width. The launch grid still uses args.ncols_max.
+        const int     J_max         = ggml_cuda_mmq_get_J_max(type, fallback, cc, 128);
+        const int64_t ncols_typical = (args.ncols_dst + args.nchannels_x - 1) / args.nchannels_x;
+        if (ncols_typical >= 1 && ncols_typical < J_max && ncols_typical < ncols_picker) {
+            ncols_picker = ncols_typical;
+        }
+    }
+
     int J_best        = 0;
     int ntiles_J_best = INT_MAX;
 
@@ -1485,7 +1505,7 @@ void mul_mat_q_switch_J(ggml_backend_cuda_context & ctx, const mmq_args & args,
             continue;
         }
 
-        const int ntiles_x = (args.ncols_max + config.J - 1) / config.J;
+        const int ntiles_x = (ncols_picker + config.J - 1) / config.J;
 
         if (ntiles_x < ntiles_J_best) {
             J_best = J;