Implement CFG_CENTER primitives

README.md

@@ -66,7 +66,7 @@ on [arXiv](https://arxiv.org/abs/1903.10407).
   - Currently supported:
   - xc7 and xcup: LUTs (including fractured), FFs, DRAM (only RAM64X1D), carry (XORCY and MUXCY or CARRY4), SRL16E and SRLC32E (no cascading), BRAM and IO
   - xcup: OSERDESE3, ISERDESE3, IDDRE1, ODDRE1, IDELAYE3, ODELAYE3, IDELAYCTRL, BUFGCTRL, BUFG, BUFGCE, BUFG_PS, PLLE4_ADV, PLLE4_BASIC, MMCME4_ADV, MMCME4_BASIC, URAM288E, DSP48E2 (no cascading)
-  - xc7: OSERDESE2, ISERDESE2, IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL, BUFGCTRL, BUFG, PLLE2_BASIC, PLLE2_ADV, DSP48E1 (cascading works)
+  - xc7: OSERDESE2, ISERDESE2, IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL, BUFGCTRL, BUFG, PLLE2_BASIC, PLLE2_ADV, DSP48E1 (cascading works), STARTUPE2, BSCANE2, ICAPE2, DCIRESET, DNA_PORT, EFUSE_USR, FRAME_ECCE2, USR_ACCESSE2
 
   - Bels, tile wires and pips are deduplicated but nodes (connections between tile wires) are not. This means
     that databases for larger devices will be several gigabytes in size (but significantly smaller than a fully flat database).

common/kernel/context.h

@@ -60,6 +60,26 @@ struct Context : Arch, DeterministicRNG
     delay_t getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &sink) const;
     DelayQuad getNetinfoRouteDelayQuad(const NetInfo *net_info, const PortRef &sink) const;
 
+    bool net_is_constant(NetInfo *net, bool &value)
+    {
+        auto gnd = this->id("$PACKER_GND_NET");
+        auto vcc = this->id("$PACKER_VCC_NET");
+        if (net == nullptr)
+            return false;
+        if (net->name.in(gnd, vcc)) {
+            value = (net->name == vcc);
+            return true;
+        } else {
+            return false;
+        }
+    }
+
+    bool net_is_constant(NetInfo *net)
+    {
+        bool unused;
+        return net_is_constant(net, unused);
+    }
+
     // provided by router1.cc
     bool checkRoutedDesign() const;
     bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr,

xilinx/constids.inc

@@ -279,6 +279,8 @@ X(AREG)
 X(BEL)
 X(BITSLICE_CONTROL_BEL)
 X(BREG)
+X(BSCAN)
+X(BSCANE2)
 X(BUFG)
 X(BUFG_BUFG)
 X(BUFG_PS)
@@ -342,6 +344,8 @@ X(DATA_RATE)
 X(DATA_RATE_OQ)
 X(DATA_RATE_TQ)
 X(DATA_WIDTH)
+X(DCIRESET)
+X(DCIRESET_DCIRESET)
 X(DCITERMDISABLE)
 X(DCLK)
 X(DDLY)
@@ -363,6 +367,8 @@ X(DIPBDIP0)
 X(DIPBDIP1)
 X(DLY_TEST_IN)
 X(DMONITORCLK)
+X(DNA_PORT)
+X(DNA_PORT_DNA_PORT)
 X(DOA_REG)
 X(DOB_REG)
 X(DPO)
@@ -372,6 +378,8 @@ X(DWE)
 X(E)
 X(ECCPIPECE)
 X(ECCPIPECEL)
+X(EFUSE_USR)
+X(EFUSE_USR_EFUSE_USR)
 X(ENARDEN)
 X(ENBWREN)
 X(EN_A)
@@ -389,6 +397,9 @@ X(FIFO18E1)
 X(FIFO18E2)
 X(FIFO36E1)
 X(FIFO36E2)
+X(FRAME_ECCE2)
+X(FRAME_ECC)
+X(FRAME_ECC_FRAME_ECC)
 X(G)
 X(GND)
 X(GTGREFCLK)
@@ -431,6 +442,10 @@ X(IBUFE3)
 X(IBUF_ANALOG)
 X(IBUF_IBUFDISABLE)
 X(IBUF_INTERMDISABLE)
+X(ICAPE2)
+X(ICAP)
+X(ICAP_ICAP)
+X(ICAP_WIDTH)
 X(IDATAIN)
 X(IDDR)
 X(IDDRE1)
@@ -508,6 +523,7 @@ X(IS_S1_INVERTED)
 X(IS_SR_INVERTED)
 X(IS_S_INVERTED)
 X(IS_WCLK_INVERTED)
+X(JTAG_CHAIN)
 X(LDCE)
 X(LDPE)
 X(LDPIPEEN)
@@ -585,6 +601,7 @@ X(PLLE3_BASE)
 X(PLLE4_ADV)
 X(PLLE4_BASIC)
 X(PRE)
+X(PROG_USR)
 X(PS8)
 X(PSCLK)
 X(PSEN)
@@ -678,6 +695,9 @@ X(SRLC32E)
 X(SRTYPE)
 X(SRVAL_OQ)
 X(SRVAL_TQ)
+X(STARTUPE2)
+X(STARTUP)
+X(STARTUP_STARTUP)
 X(SYSMONE1)
 X(SYSMONE4)
 X(T)
@@ -704,6 +724,10 @@ X(TX_RST_DLY)
 X(T_OUT)
 X(URAM288_BASE)
 X(USE_DPORT)
+X(USR_ACCESSE2)
+X(USR_ACCESS)
+X(USR_ACCESS_USR_ACCESS)
+X(USRCCLKO)
 X(VCC)
 X(VREF)
 X(VTC_RDY)

xilinx/fasm.cc

@@ -1157,6 +1157,50 @@ struct FasmBackend
         }
     }
 
+    void write_cfg()
+    {
+        for (auto &cell : ctx->cells) {
+            CellInfo *ci = cell.second.get();
+            auto tile_name = get_tile_name(ci->bel.tile);
+            if (!boost::starts_with(tile_name, "CFG_CENTER_"))
+                continue;
+
+            push(tile_name);
+            if (ci->type == id_BSCAN) {
+                push("BSCAN");
+                int chain = int_or_default(ci->params, id_JTAG_CHAIN, 1);
+                if (chain < 1 || 4 < chain)
+                    log_error("Invalid JTAG_CHAIN number of '%d\n'. Allowed values are: 1-4.", chain);
+                write_bit("JTAG_CHAIN_" + std::to_string(chain));
+                pop();
+            }
+
+            if (ci->type == id_DCIRESET_DCIRESET) {
+                write_bit("DCIRESET.ENABLED");
+            }
+
+            if (ci->type == id_ICAP_ICAP) {
+                push("ICAP");
+                std::string width = str_or_default(ci->params, id_ICAP_WIDTH, "X32");
+                if (width != "X32" && width != "X16" && width != "X8")
+                    log_error("Unknown ICAP_WIDTH of '%s\n'. Allowed values are: X32, X16 and X8.", width.c_str());
+                if (width == "X16") write_bit("ICAP_WIDTH_X16");
+                if (width == "X8") write_bit("ICAP_WIDTH_X8");
+                pop();
+            }
+
+            if (ci->type == id_STARTUP_STARTUP) {
+                std::string prog_usr = str_or_default(ci->params, id_PROG_USR, "FALSE");
+                if (prog_usr != "TRUE" && prog_usr != "FALSE")
+                    log_error("Invalid PROG_USR attribute in STARTUPE2 of '%s\n'. Allowed values are: TRUE, FALSE.", prog_usr.c_str());
+                write_bit("STARTUP.PROG_USR", prog_usr == "TRUE");
+                write_bit("STARTUP.USRCCLKO_CONNECTED", !ctx->net_is_constant(ci->getPort(id_USRCCLKO)));
+            }
+
+            pop();
+        }
+    }
+
     std::vector<std::string> used_wires_starting_with(int tile, const std::string &prefix, bool is_source)
     {
         std::vector<std::string> wires;
@@ -1618,6 +1662,7 @@ struct FasmBackend
     {
         get_invertible_pins(ctx, invertible_pins);
         write_logic();
+        write_cfg();
         write_io();
         write_routing();
         write_bram();

xilinx/pack.cc

@@ -894,6 +894,7 @@ bool Arch::pack()
         packer.pack_constants();
         packer.pack_iologic();
         packer.pack_idelayctrl();
+        packer.pack_cfg();
         packer.pack_clocking();
         packer.pack_muxfs();
         packer.pack_carries();

xilinx/pack.h

@@ -231,6 +231,9 @@ struct XC7Packer : public XilinxPacker
     void pack_gbs();
     void pack_clocking();
 
+    // CFG
+    void pack_cfg();
+
     // BRAM
     void pack_bram();
 

xilinx/pack_clocking_xc7.cc

@@ -130,6 +130,22 @@ void XC7Packer::pack_gbs()
     }
 }
 
+void XC7Packer::pack_cfg()
+{
+    log_info("Packing cfg...\n");
+    dict<IdString, XFormRule> cfg_rules;
+    cfg_rules[id_BSCANE2].new_type      = id_BSCAN;
+    cfg_rules[id_DCIRESET].new_type     = id_DCIRESET_DCIRESET;
+    cfg_rules[id_DNA_PORT].new_type     = id_DNA_PORT_DNA_PORT;
+    cfg_rules[id_EFUSE_USR].new_type    = id_EFUSE_USR_EFUSE_USR;
+    cfg_rules[id_ICAPE2].new_type       = id_ICAP_ICAP;
+    cfg_rules[id_FRAME_ECCE2].new_type  = id_FRAME_ECC_FRAME_ECC;
+    cfg_rules[id_STARTUPE2].new_type    = id_STARTUP_STARTUP;
+    cfg_rules[id_USR_ACCESSE2].new_type = id_USR_ACCESS_USR_ACCESS;
+
+    generic_xform(cfg_rules);
+}
+
 void XC7Packer::pack_clocking()
 {
     pack_plls();