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added digilent genesys2 (kintex7) example #13

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added digilent genesys2 (kintex7) example #13

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951646d
added digilent genesys2 (kintex7) example
Feb 17, 2020
a06740d
code update
Feb 17, 2020
d211422
Update simpleCircuit.sh
asanaullah Feb 19, 2020
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30 changes: 30 additions & 0 deletions xilinx/examples/genesys2/Genesys2.xdc
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set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
set_property IOSTANDARD LVCMOS33 [get_ports led[4]]

set_property LOC T28 [get_ports led[0]]
set_property LOC V19 [get_ports led[1]]
set_property LOC U30 [get_ports led[2]]
set_property LOC U29 [get_ports led[3]]
set_property LOC V20 [get_ports led[4]]


set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]

set_property LOC G19 [get_ports sw[0]]
set_property LOC G25 [get_ports sw[1]]
set_property LOC H24 [get_ports sw[2]]
set_property LOC K19 [get_ports sw[3]]
set_property LOC N19 [get_ports sw[4]]
set_property LOC P19 [get_ports sw[5]]
set_property LOC P26 [get_ports sw[6]]
set_property LOC P27 [get_ports sw[7]]
21 changes: 21 additions & 0 deletions xilinx/examples/genesys2/kintex7patch.py
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import json
import sys
NextPnrFile = sys.argv[1]
input_file = open(NextPnrFile, 'r')
data = json.loads(input_file.read())
input_file.close();

for cells in data['modules']['top']['cells']:
if (data['modules']['top']['cells'][cells]['type'] == 'PAD'):
data['modules']['top']['cells'][cells]['type'] = 'IOB_PAD'

if (data['modules']['top']['cells'][cells]['type'] == 'IOB33_INBUF_EN' or data['modules']['top']['cells'][cells]['type'] == 'IOB33_OUTBUF'):
first_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/')
if (first_inst >= 0):
second_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/',1+first_inst)
if (second_inst >= 0):
data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']=data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'][:first_inst]+data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'][second_inst:];

output_file = open(NextPnrFile, 'w')
output_file.write(json.dumps(data,indent = 5, sort_keys=True))
output_file.close()
7 changes: 7 additions & 0 deletions xilinx/examples/genesys2/simpleCircuit.sh
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#!/usr/bin/env bash
set -ex
yosys -p "synth_xilinx -flatten -arch xc7 -nobram -nowidelut -top top; write_json simpleCircuit.json" simpleCircuit.v
../../../nextpnr-xilinx --chipdb ../../xc7k325t.bin --json simpleCircuit.json --xdc Genesys2.xdc --write simpleCircuit_routed.json
python kintex7patch.py simpleCircuit_routed.json
java -jar ../../../rapidwright_json2dcp.jar xc7k325tffg900-2 simpleCircuit_routed.json simpleCircuit.dcp
vivado -mode batch -nojournal -nolog -source simpleCircuit.tcl
4 changes: 4 additions & 0 deletions xilinx/examples/genesys2/simpleCircuit.tcl
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open_checkpoint simpleCircuit.dcp
write_verilog -force simpleCircuit_out.v
set_property IS_LOC_FIXED true [get_ports]
write_bitstream -force simpleCircuit.bit
5 changes: 5 additions & 0 deletions xilinx/examples/genesys2/simpleCircuit.v
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module top (input [7:0] sw, output [4:0] led);

assign led = {1'b0,sw[3:0]} + {1'b0,sw[7:4]};

endmodule