Router2 fails to converge on XC7A100 and XC7A200

[cestrauss]

Router2 enters a seemingly infinite loop on one of my designs, for XC7A100. I systematically deleted ranges of cells from the input JSON until I reduced it to just three nets and three cells: two LUT1 and a FDCE in a loop. XC7A200 also shows the problem, but XC7A35 and XC7A50 complete successfully. Router1 doesn't seem to be affected.
Git commit is current "xilinx-upstream" branch, f793875.
Reduced design: top.json
Shell build script: build.txt
Log output: top_tim.txt
Log output (debug): top_debug_tim.txt

[lehaifeng000]

why there is 2 LUT1 ? I think it should be optimized by abc9...

[lehaifeng000]

and there is no iopad and buf?

[cestrauss]

Sorry, it was not created by Yosys, it was hand edited by me.

Here follows the full design, which really was created by Yosys: top.zip

It fails to converge with Router2.