Merge pull request #5 from openXC7/master

Add CFG_CENTER tile primitives
gatecat · Oct 14, 2023 · 57de921 · 57de921
2 parents d8f5e4f + 7607325
commit 57de921
Show file tree

Hide file tree

Showing 32 changed files with 8,364 additions and 0 deletions.
diff --git a/artix7/site_type_BSCAN.json b/artix7/site_type_BSCAN.json
@@ -0,0 +1,114 @@
+{
+  "BSCAN": {
+    "bels": {
+      "BSCAN": {
+        "type": "BSCAN",
+        "class": "BEL",
+        "pins": {
+          "CAPTURE": {
+          "dir": "OUTPUT",
+          "wire": "CAPTURE"
+          },
+          "DRCK": {
+          "dir": "OUTPUT",
+          "wire": "DRCK"
+          },
+          "RESET": {
+          "dir": "OUTPUT",
+          "wire": "RESET"
+          },
+          "RUNTEST": {
+          "dir": "OUTPUT",
+          "wire": "RUNTEST"
+          },
+          "SEL": {
+          "dir": "OUTPUT",
+          "wire": "SEL"
+          },
+          "SHIFT": {
+          "dir": "OUTPUT",
+          "wire": "SHIFT"
+          },
+          "TCK": {
+          "dir": "OUTPUT",
+          "wire": "TCK"
+          },
+          "TDI": {
+          "dir": "OUTPUT",
+          "wire": "TDI"
+          },
+          "TDO": {
+          "dir": "INPUT",
+          "wire": "TDO"
+          },
+          "TMS": {
+          "dir": "OUTPUT",
+          "wire": "TMS"
+          },
+          "UPDATE": {
+          "dir": "OUTPUT",
+          "wire": "UPDATE"
+          }
+        }
+      }
+    },
+    "pips": [],
+    "pins": {
+      "CAPTURE": {
+        "primary": "CAPTURE",
+        "wire": "CAPTURE",
+        "dir": "OUTPUT"
+      },
+      "DRCK": {
+        "primary": "DRCK",
+        "wire": "DRCK",
+        "dir": "OUTPUT"
+      },
+      "RESET": {
+        "primary": "RESET",
+        "wire": "RESET",
+        "dir": "OUTPUT"
+      },
+      "RUNTEST": {
+        "primary": "RUNTEST",
+        "wire": "RUNTEST",
+        "dir": "OUTPUT"
+      },
+      "SEL": {
+        "primary": "SEL",
+        "wire": "SEL",
+        "dir": "OUTPUT"
+      },
+      "SHIFT": {
+        "primary": "SHIFT",
+        "wire": "SHIFT",
+        "dir": "OUTPUT"
+      },
+      "TCK": {
+        "primary": "TCK",
+        "wire": "TCK",
+        "dir": "OUTPUT"
+      },
+      "TDI": {
+        "primary": "TDI",
+        "wire": "TDI",
+        "dir": "OUTPUT"
+      },
+      "TDO": {
+        "primary": "TDO",
+        "wire": "TDO",
+        "dir": "INPUT"
+      },
+      "TMS": {
+        "primary": "TMS",
+        "wire": "TMS",
+        "dir": "OUTPUT"
+      },
+      "UPDATE": {
+        "primary": "UPDATE",
+        "wire": "UPDATE",
+        "dir": "OUTPUT"
+      }
+    }
+  }
+}
diff --git a/artix7/site_type_DCIRESET.json b/artix7/site_type_DCIRESET.json
@@ -0,0 +1,33 @@
+{
+  "DCIRESET": {
+    "bels": {
+      "DCIRESET": {
+        "type": "DCIRESET_DCIRESET",
+        "class": "BEL",
+        "pins": {
+          "LOCKED": {
+              "dir": "OUTPUT",
+              "wire": "LOCKED"
+          },
+          "RST": {
+            "dir": "INPUT",
+            "wire": "RST"
+          }
+        }
+      }
+    },
+    "pips": [],
+    "pins": {
+      "LOCKED": {
+        "primary": "LOCKED",
+        "wire": "LOCKED",
+          "dir": "OUTPUT"
+      },
+      "RST": {
+        "primary": "RST",
+        "wire": "RST",
+        "dir": "INPUT"
+      }
+    }
+  }
+}
diff --git a/artix7/site_type_DNA_PORT.json b/artix7/site_type_DNA_PORT.json
@@ -0,0 +1,60 @@
+{
+  "DNA_PORT": {
+    "bels": {
+      "DNA_PORT": {
+        "type": "DNA_PORT_DNA_PORT",
+        "class": "BEL",
+        "pins": {
+          "DOUT": {
+              "dir": "OUTPUT",
+              "wire": "DOUT"
+          },
+          "CLK": {
+            "dir": "INPUT",
+            "wire": "CLK"
+          },
+          "DIN": {
+            "dir": "INPUT",
+            "wire": "DIN"
+          },
+          "READ": {
+            "dir": "INPUT",
+            "wire": "READ"
+          },
+          "SHIFT": {
+            "dir": "INPUT",
+            "wire": "SHIFT"
+          }
+        }
+      }
+    },
+    "pips": [],
+    "pins": {
+      "DOUT": {
+        "primary": "DOUT",
+        "wire": "DOUT",
+        "dir": "OUTPUT"
+      },
+      "CLK": {
+        "primary": "CLK",
+        "wire": "CLK",
+        "dir": "INPUT"
+      },
+      "DIN": {
+        "primary": "DIN",
+        "wire": "DIN",
+        "dir": "INPUT"
+      },
+      "READ": {
+        "primary": "READ",
+        "wire": "READ",
+        "dir": "INPUT"
+      },
+      "SHIFT": {
+        "primary": "SHIFT",
+        "wire": "SHIFT",
+        "dir": "INPUT"
+      }
+    }
+  }
+}