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cake_grouped_fp8_gemm is Cake's prepared contiguous grouped FP8 GEMM. On sm_100a and sm_103a it ships three variants: FP32-scale programs, block-scaled programs with packed UE8M0 scales, and a fused gate_up + SwiGLU + FP8 quant form. On sm_107a it ships only the block-scaled UE8M0 variant, and this PR changes only that variant. The two sm_107a BLOCK_N 128 block-scaled programs, used by the single-run route and the per-32-row-run route, previously loaded the packed UE8M0 scale word once per K block. Because one word holds the scales of 4 K blocks, they now load each word once per 4 K blocks and prefetch the next word one group ahead. As a result, the MMA warp no longer waits on a scale load for every K block. Output bits are identical to the previous programs, and the host routes are unchanged. The other three sm_107a programs are rebuilt under new names with unchanged code. The baseline is the previous Cake program on the same route.
Shape
route
M, N, K
G
alignment
valid rows
before µs (216)
this PR µs (216)
speedup (216)
before µs (212)
this PR µs (212)
speedup (212)
corr_empty_tail_k128 *
bs_ue8m0_n128
1664, 384, 128
8
128
556
4.77
4.77
1.0000
4.61
4.61
1.0000
corr_n256_wide_k4096
bs_ue8m0_n128
1664, 256, 4096
5
128
1028
11.81
10.50
1.1280
11.71
10.40
1.1261
q397b_gate_up_b64_a128
bs_ue8m0_n128
65664, 512, 4096
512
128
640
91.55
91.01
1.0059
81.98
80.62
1.0163
q397b_gate_up_t1_a128
bs_ue8m0_n128
65152, 512, 4096
512
128
10
15.26
14.05
1.0783
15.04
13.98
1.0750
q397b_gate_up_t256_a128
bs_ue8m0_n128
67584, 512, 4096
512
128
2560
125.33
124.10
1.0100
111.97
109.31
1.0212
q397b_gate_up_t32_a128
bs_ue8m0_n128
65408, 512, 4096
512
128
320
66.75
65.79
1.0141
60.88
59.26
1.0270
q397b_gate_up_t512_a128
bs_ue8m0_n128
70144, 512, 4096
512
128
5120
125.36
124.23
1.0088
111.89
109.62
1.0221
q397b_gate_up_t8_a128
bs_ue8m0_n128
65152, 512, 4096
512
128
80
30.94
30.37
1.0244
29.22
28.42
1.0317
corr_run32_a32 *
bs_ue8m0_n128_run32
640, 1024, 256
8
32
297
6.83
6.82
1.0047
6.43
6.43
1.0050
corr_run32_a64 *
bs_ue8m0_n128_run32
1152, 256, 512
8
64
565
6.59
6.53
1.0070
6.78
6.74
1.0048
corr_run32_a96 *
bs_ue8m0_n128_run32
1152, 384, 128
6
96
487
6.18
6.14
1.0052
5.79
5.76
1.0055
q35b_gate_up_b8_a32
bs_ue8m0_n128_run32
8064, 1024, 2048
256
32
64
25.09
24.72
1.0148
23.87
23.23
1.0289
q397b_gate_up_b16_a32
bs_ue8m0_n128_run32
16128, 512, 4096
512
32
160
46.34
45.67
1.0101
42.66
41.60
1.0276
q397b_gate_up_b2_a32
bs_ue8m0_n128_run32
16000, 512, 4096
512
32
20
36.85
30.08
1.2306
35.86
29.76
1.2054
q397b_gate_up_b4_a32
bs_ue8m0_n128_run32
16000, 512, 4096
512
32
40
38.10
32.22
1.1822
37.15
31.30
1.1871
q397b_gate_up_b8_a32
bs_ue8m0_n128_run32
16000, 512, 4096
512
32
80
39.94
37.54
1.0656
39.23
35.95
1.0919
GPU products NVIDIA R200 (216 SMs) and VR200 (212 SMs), architecture sm_107a, CUDA 13.4. G is the number of experts. Before = the previous Cake program on the route, this PR = the program with scale-word reuse. Each value is the median over operand seeds 21, 22 and 23, with L2 flushed and before/after runs paired and interleaved. Speedup = 1 / (median over seeds of the paired after/before ratio); above 1 is faster. The four rows marked * (corr_empty_tail_k128, corr_run32_a32, corr_run32_a64, corr_run32_a96) are within the measured run-to-run noise.
sm_100a and sm_103a are unchanged; the family ships on sm_100a, sm_103a and sm_107a.
Summary by CodeRabbit
Improvements
Updated grouped FP8 GEMM execution paths for supported hardware. Scale data is reused across groups of K tiles, with existing boundary handling retained.
Tests
Expanded coverage for K dimensions spanning one to nine blocks, including cases that do not align to four-block scale groups.
Added checks comparing results with a reference and, where applicable, an alternate block-size route.
…cked UE8M0 scale word once per 4 K blocks
On sm_107a the two BLOCK_N 128 block-scaled programs (single-run and
per-32-row-run) now keep each packed UE8M0 scale word in registers for
the 4 K blocks it covers and load the next word one group ahead, so the
MMA warp no longer waits on a scale load for every K block. Outputs are
bitwise those of the previous programs.
The three other sm_107a programs (BLOCK_N 256 single-run, per-32-row-run
and lead-prefetch) are re-generated under new names with unchanged
sources. sm_100a and sm_103a are unchanged.
Adds a test of the BLOCK_N 128 routes at K of 1 to 9 K blocks.
@flashinfer-bot run tests/gemm/test_cake_group_gemm_fp8_nt_groupwise_contiguous.py tests/gemm/test_cake_group_gemm_fp8_nt_groupwise_contiguous_silu_quant.py tests/gemm/test_groupwise_scaled_gemm_fp8.py
The SM107a grouped FP8 GEMM updates add scale-word caching to two kernel variants, update program bindings and JIT routes, and add tests for K dimensions that cover partial packed scale words.
Changes: SM107a grouped FP8 GEMM
Layer / File(s)
Summary
Cache scale words across K tiles csrc/cake_grouped_fp8_gemm/*_kernel.cu
Two kernel variants load SFA and SFB scale words in groups of four K tiles, reuse the cached words during scale staging, and preload the next group when available.
Register and route SM107a programs csrc/cake_grouped_fp8_gemm/*_binding.cu, csrc/cake_grouped_fp8_gemm/*_kernel.cu, flashinfer/jit/gemm/cake_grouped_fp8_gemm.py
Kernel symbols and binding references are updated. SM107a program and module registrations change, and five routes point to new program IDs.
Test partial packed scale-word coverage tests/gemm/test_cake_group_gemm_fp8_nt_groupwise_contiguous.py
New SM107a test cases cover multiple K dimensions. They check BLOCK_N 128 results against a reference and compare output bits with BLOCK_N 256 for single-run layouts.
flashinfer-ai/flashinfer#8881: Adds an SM107a lead-prefetch program and regenerates BLOCK_N 128 programs, which are also updated in this PR.
Suggested reviewers:yzh119
Merge Risk: Minimal · up to 976e5
No actionable merge-blocking issue is identified in the SM107a scale-caching changes. Merge after normal checks, including the requested GPU tests, pass.
Pre-merge checks: 3 · 2
Failed checks: 2 warnings
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Docstring Coverage
Docstring coverage is 9.09% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff with cyclomatic complexity of at least 2. Documentat…
Write docstrings for the functions missing them to satisfy the coverage threshold.
Passed checks: 3 passed
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The title clearly identifies the main SM107a scale-word reuse change.
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Write docstrings for the functions missing them to satisfy the coverage threshold.
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only still-valid issues, skip the rest with a brief reason, keep changes
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Add the template sections. Link related issues or state that none apply. Report
the pre-commit checks and test results, or state that they are pending. Include
the experimental track section unchanged for a normal PR.
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Write docstrings for the functions missing them to satisfy the coverage
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…ashinfer-ai#8972, mega_moe_v3) into cake-lm-head-nondet-train
Resolve tests/test_helpers/cake_package.py: keep this branch's LM-head
det/nondet PACKAGES rows and the dense GEMM det/nondet rows from flashinfer-ai#8926.
…K_N 256 single-run layouts (#8979)
`cake_grouped_fp8_gemm` is Cake's prepared contiguous grouped FP8 GEMM.
On sm_100a and sm_103a it ships three variants: FP32-scale programs,
block-scaled programs with packed UE8M0 scales, and a fused gate_up +
SwiGLU + FP8 quant form. On sm_107a it ships only the block-scaled UE8M0
variant. This PR changes only the sm_107a host route rule and does not
change kernel code. It follows #8972, which shipped the current sm_107a
programs. The host sends some layouts to the BLOCK_N 256 single-run
program. In two more cases, those layouts now take the existing
lead-prefetch program instead: K at most 256 with at most 10 routed rows
per group, and K above 256 with at least 160 routed rows per group. The
lead-prefetch program is the same program, except that it reads each
tile's leading row index from a shared-memory table filled at kernel
entry. The previous lead-prefetch cases are unchanged. Output bits are
identical to the BLOCK_N 256 single-run program. The baseline is the
previous Cake route for these shapes: the BLOCK_N 256 single-run program
without the table.
| Shape | M, N, K | G | routed rows per group | before µs (216) | this
PR µs (216) | speedup (216) | before µs (212) | this PR µs (212) |
speedup (212) |
|---|---|---|---|---|---|---|---|---|---|
| q397b_down_b64_a128 | 65664, 4096, 256 | 512 | 1.25 | 57.74 | 55.36 |
1.0387 | 54.69 | 52.74 | 1.0370 |
| q397b_down_t256_a128 | 67584, 4096, 256 | 512 | 5 | 74.27 | 71.74 |
1.0335 | 70.14 | 67.90 | 1.0339 |
| q397b_down_t512_a128 | 70144, 4096, 256 | 512 | 10 | 74.99 | 72.08 |
1.0422 | 70.59 | 67.90 | 1.0396 |
| fib_q35b_gate_up_t16384 | 163584, 1024, 2048 | 256 | 512 | 156.37 |
150.80 | 1.0369 | 150.18 | 144.85 | 1.0368 |
| q35b_down_t16384_a128 | 163584, 2048, 512 | 256 | 512 | 108.90 |
101.55 | 1.0723 | 105.84 | 103.14 | 1.0267 |
| q35b_down_t8192_a128 | 98048, 2048, 512 | 256 | 256 | 68.80 | 65.18 |
1.0555 | 65.74 | 62.32 | 1.0547 |
| q35b_gate_up_t16384_a128 | 163584, 1024, 2048 | 256 | 512 | 154.59 |
149.44 | 1.0342 | 148.43 | 143.68 | 1.0327 |
| q35b_gate_up_t8192_a128 | 98048, 1024, 2048 | 256 | 256 | 98.96 |
97.58 | 1.0141 | 92.64 | 90.91 | 1.0191 |
| q397b_gate_up_t16384_a128 (parity) | 228864, 512, 4096 | 512 | 320 |
233.67 | 233.57 | 1.0001 | 208.48 | 206.32 | 1.0114 |
| q397b_gate_up_t8192_a128 (parity) | 146944, 512, 4096 | 512 | 160 |
172.00 | 171.75 | 1.0021 | 153.22 | 152.54 | 1.0044 |
GPU products NVIDIA R200 (216 SMs) and VR200 (212 SMs), architecture
sm_107a, CUDA 13.4. G is the number of experts. "Before" is the previous
Cake route, the BLOCK_N 256 single-run program. "This PR" is the
lead-prefetch program. Each value is the median over three operand
seeds, with L2 flushed and before/after runs paired and interleaved. The
seeds are 41, 42 and 43 on the 216-SM board and 31, 32 and 33 on the
212-SM board. Speedup = 1 / (median over seeds of the paired
after/before ratio); above 1 is faster. The two rows marked parity
(q397b_gate_up_t16384_a128, q397b_gate_up_t8192_a128) are within the
parity band, not faster. They are listed because the route rule moves
them too, and they are kept on the new route so the rule stays
consistent. The other eight rows are faster on both boards.
sm_100a and sm_103a are unchanged; the family ships on sm_100a, sm_103a
and sm_107a.
<!-- This is an auto-generated comment: release notes by coderabbit.ai
-->
<!-- coderabbit-ai-generated:v1 -->
## Summary by CodeRabbit
* **Performance**
* Improved selection of optimized processing paths for grouped FP8
matrix multiplication across a wider range of eligible workloads.
* **Tests**
* Added coverage for selection boundaries and cases where the optimized
path should not be selected.
<!-- end of auto-generated comment: release notes by coderabbit.ai -->
---------
Co-authored-by: Yingyi Huang <averyh@nvidia.com>
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cake_grouped_fp8_gemmis Cake's prepared contiguous grouped FP8 GEMM. On sm_100a and sm_103a it ships three variants: FP32-scale programs, block-scaled programs with packed UE8M0 scales, and a fused gate_up + SwiGLU + FP8 quant form. On sm_107a it ships only the block-scaled UE8M0 variant, and this PR changes only that variant. The two sm_107a BLOCK_N 128 block-scaled programs, used by the single-run route and the per-32-row-run route, previously loaded the packed UE8M0 scale word once per K block. Because one word holds the scales of 4 K blocks, they now load each word once per 4 K blocks and prefetch the next word one group ahead. As a result, the MMA warp no longer waits on a scale load for every K block. Output bits are identical to the previous programs, and the host routes are unchanged. The other three sm_107a programs are rebuilt under new names with unchanged code. The baseline is the previous Cake program on the same route.GPU products NVIDIA R200 (216 SMs) and VR200 (212 SMs), architecture sm_107a, CUDA 13.4. G is the number of experts. Before = the previous Cake program on the route, this PR = the program with scale-word reuse. Each value is the median over operand seeds 21, 22 and 23, with L2 flushed and before/after runs paired and interleaved. Speedup = 1 / (median over seeds of the paired after/before ratio); above 1 is faster. The four rows marked * (corr_empty_tail_k128, corr_run32_a32, corr_run32_a64, corr_run32_a96) are within the measured run-to-run noise.
sm_100a and sm_103a are unchanged; the family ships on sm_100a, sm_103a and sm_107a.
Summary by CodeRabbit