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perf(cake_gated_act_mxfp8): band-path programs for three SM107 entries - #7783

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yyihuang:cake-gated-act-mxfp8-sm107-band-forms

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@yyihuang yyihuang commented Oct 28, 2026 •

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The Cake fused SwiGLU + MXFP8 quantization kernel computes silu(gate) * up from a BF16 input [M, 2K] and quantizes the result to MXFP8. Each group of 32 E4M3 values gets one E8M0 scale (RCEIL rounding), and the scales are stored in the swizzled 128 x 4 layout. The kernel has one data type and six forms. The forward form is flashinfer.silu_and_mul_mxfp8_quantize, with output [M, K]. The backward form is flashinfer.silu_and_mul_mxfp8_quantize_backward. It computes the gate and up gradients [M, 2K] from the input [M, 2K] and grad_output [M, K], and quantizes them to MXFP8 in the same way. Each one can write rowwise, colwise or both outputs. flashinfer.cake_gated_act_mxfp8_backend runs one program per call and picks it by M * K for each architecture.

This PR changes program selection on sm_107a (R200) only. On R200, four rows are 1.020x to 1.047x faster with block-scaled inputs than the previous Cake version. Three M * K dispatch ranges move to the band-path forms from #7492, and two of them also use the packed f32x2 sigmoid from #7396. Forward rowwise in [2^24, 2^26) now runs the two-row form with the called band path at 4 CTAs per SM. Backward rowwise in [2^18, 2^26) runs the packed-sigmoid form with the called band path at 8 CTAs per SM. Backward colwise in [2^23, 2^24) runs the packed-sigmoid form with the ffs band path at 8 CTAs per SM. The package goes from 57 to 60 programs. The backward rowwise packed-sigmoid program no longer ships for sm_107a but still serves sm_103a. Outputs are byte-identical to the previous version, and the public API is unchanged.

The baseline is the previous Cake version of this kernel, which is the package from #7770. The method is the same as in #7770, with 8 paired rounds. Both versions run in the same process on the same GPU, in alternating paired runs, with a cold L2 before every launch. Each table row is one shape and pass. There are two column groups: unit-normal inputs, and block-scaled inputs (normals with per-32-block scales spread over a wide exponent range). Each speedup sits next to both latencies. Speedup is previous Cake latency divided by this PR's latency. Latency is the mean, over the paired samples, of each sample's median CUPTI kernel time per call, in microseconds. A speedup above 1 means this PR is faster.

Four R200 rows change program. With block-scaled inputs, all four are faster than the run-to-run (A/A) spread: 1.047x (4096 x 2048 backward colwise), 1.042x (4096 x 7168 forward rowwise), 1.031x (4096 x 2048 backward rowwise) and 1.020x (4096 x 7168 backward rowwise). The other 26 block-scaled rows stay within the spread, and block-scaled ratios range from 0.999x to 1.047x. With unit-normal inputs, all 30 rows are ties within the spread, from 0.999x to 1.001x. No row is slower than the spread. The table covers R200 (sm_107a, 208 SMs) on CUDA 13.4, with five shapes and six passes. The measured package has the same machine code as the package in this PR. There are no B200 or GB300 tables because the sm_100a and sm_103a programs have the same machine code as in the previous version.

NVIDIA R200 (sm_107a, 208 SMs), CUDA 13.4

M x K Pass Unit normals: previous Cake (µs) This PR (µs) Speedup Block-scaled: previous Cake (µs) This PR (µs) Speedup
128 x 128 fwd rowwise 2.11 2.11 1.000x 2.25 2.25 1.002x
128 x 128 fwd colwise 2.26 2.26 1.000x 2.41 2.41 0.999x
128 x 128 fwd both 2.34 2.33 1.001x 2.64 2.64 0.999x
128 x 128 bwd rowwise 2.04 2.04 1.000x 2.26 2.26 1.000x
128 x 128 bwd colwise 2.15 2.15 1.001x 2.24 2.23 1.002x
128 x 128 bwd both 2.27 2.27 0.999x 2.40 2.40 1.001x
4096 x 2048 fwd rowwise 7.15 7.15 1.000x 8.20 8.17 1.004x
4096 x 2048 fwd colwise 7.30 7.29 1.000x 8.75 8.74 1.000x
4096 x 2048 fwd both 8.71 8.71 1.000x 10.32 10.30 1.002x
4096 x 2048 bwd rowwise 10.53 10.52 1.001x 11.01 10.68 1.031x
4096 x 2048 bwd colwise 11.05 11.04 1.001x 12.28 11.73 1.047x
4096 x 2048 bwd both 13.24 13.24 1.000x 13.88 13.85 1.002x
4096 x 7168 fwd rowwise 18.39 18.37 1.001x 20.37 19.55 1.042x
4096 x 7168 fwd colwise 18.83 18.82 1.000x 21.46 21.47 1.000x
4096 x 7168 fwd both 21.91 21.91 1.000x 25.80 25.79 1.000x
4096 x 7168 bwd rowwise 28.89 28.88 1.000x 29.56 28.98 1.020x
4096 x 7168 bwd colwise 28.82 28.82 1.000x 30.23 30.22 1.000x
4096 x 7168 bwd both 35.91 35.91 1.000x 36.90 36.84 1.002x
16384 x 7168 fwd rowwise 59.06 59.07 1.000x 65.89 65.91 1.000x
16384 x 7168 fwd colwise 60.41 60.41 1.000x 69.03 69.01 1.000x
16384 x 7168 fwd both 75.10 75.09 1.000x 79.41 79.41 1.000x
16384 x 7168 bwd rowwise 97.26 97.26 1.000x 101.09 101.11 1.000x
16384 x 7168 bwd colwise 99.36 99.36 1.000x 107.40 107.43 1.000x
16384 x 7168 bwd both 132.00 132.02 1.000x 134.08 133.99 1.001x
131072 x 8192 fwd rowwise 481.61 481.61 1.000x 532.50 532.46 1.000x
131072 x 8192 fwd colwise 514.00 513.99 1.000x 561.53 561.77 1.000x
131072 x 8192 fwd both 657.84 657.91 1.000x 665.77 665.79 1.000x
131072 x 8192 bwd rowwise 831.94 831.92 1.000x 864.37 864.39 1.000x
131072 x 8192 bwd colwise 864.92 864.93 1.000x 917.28 917.31 1.000x
131072 x 8192 bwd both 1183.11 1183.16 1.000x 1196.51 1196.42 1.000x

Cake has no other variants of this kernel beyond these six BF16-to-MXFP8 forms with the swizzled scale layout, and the family ships on sm_100a (B200), sm_103a (GB300) and sm_107a (R200).

Summary by CodeRabbit

  • New Features
    • Added support for gated-activation MXFP8 forward and backward operations on SM107A GPUs, including rowwise and columnwise output paths.
    • Kernel selection now varies by operation and workload size. Some smaller backward rowwise workloads on SM107A use the existing fallback route.

On sm_107a, three ranges move to band-path programs: forward rowwise in [2^24, 2^26) takes the two-row form with the
call band at 4 CTAs per SM; backward rowwise in [2^18, 2^26) takes the packed-sigmoid form with the call band at 8 CTAs
per SM; backward colwise in [2^23, 2^24) takes the packed-sigmoid form with the ffs band at 8 CTAs per SM. Outputs are
byte-identical; the public API is unchanged. The package goes from 57 to 60 programs (3 new); the backward rowwise
packed-sigmoid program no longer ships for sm_107a. sm_100a and sm_103a programs are unchanged.

Co-Authored-By: Claude <noreply@anthropic.com>
@flashinfer-bot flashinfer-bot added the op: misc norm, activation, sampling, RoPE, quantization, etc. label Oct 28, 2026
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Reviewing files that changed from the base of the PR and between 0d14819 and 42d7e27.

Files selected for processing: 8
  • flashinfer/cake_gated_act_mxfp8_backend/build.json
  • flashinfer/cake_gated_act_mxfp8_backend/cake_jit.py
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_75c68471d8a4921f432a_binding.cu
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_75c68471d8a4921f432a_kernel.cu
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_822bead4b44c749f7afe_binding.cu
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_822bead4b44c749f7afe_kernel.cu
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_f8db01d14808a5afc6da_binding.cu
  • flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_f8db01d14808a5afc6da_kernel.cu

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Walkthrough

The backend adds three SM107A gated-activation MXFP8 kernel variants and their TVM-FFI bindings. JIT routing selects variants by operation and M * K threshold. The build manifest adds library records and removes one existing SM107A record.

Changes: SM107A MXFP8 backend

Layer / File(s) Summary
Forward-row kernel and binding
flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_75c68471d8a4921f432a_kernel.cu, flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_75c68471d8a4921f432a_binding.cu
Adds an SM107A forward-row kernel with fast and fallback activation paths, row-wise E4M3 quantization, and per-region scales. Its binding validates tensors and launch dimensions, then launches the kernel.
Backward kernels and bindings
flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_822bead4b44c749f7afe_kernel.cu, flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_822bead4b44c749f7afe_binding.cu, flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_f8db01d14808a5afc6da_kernel.cu, flashinfer/cake_gated_act_mxfp8_backend/csrc/cake_gated_act_mxfp8_f8db01d14808a5afc6da_binding.cu
Adds two backward kernels that compute gated-activation gradients, use fallback calculations for selected inputs, and write E4M3 outputs with per-group scales. Their bindings validate tensors and launch parameters before launching the kernels.
JIT routing and build records
flashinfer/cake_gated_act_mxfp8_backend/cake_jit.py, flashinfer/cake_gated_act_mxfp8_backend/build.json
Adds SM107A JIT records and routes for forward-row, backward-row, and backward-col variants. The routes use thresholds of 2^24, 2^18, and 2^23, respectively. The build manifest adds three SM107A library records and removes one existing record.

Priority: Low

Estimated code review effort: 4 (Complex) | ~60 minutes

Change: Refactor

Sequence Diagram(s)

sequenceDiagram
  participant cake_jit
  participant TVM_FFI_run
  participant kernel_cake_gated_act_mxfp8_75c68471d8a4921f432a
  cake_jit->>TVM_FFI_run: Select SM107A forward-row variant when M*K >= 2^24
  TVM_FFI_run->>kernel_cake_gated_act_mxfp8_75c68471d8a4921f432a: Validate tensors and launch kernel
Loading

Suggested reviewers: sricketts, aleozlx, yongwww

Merge Risk: Minimal · up to 42d7e

This change routes three SM107A (R200) MXFP8 gated-activation ranges to new kernel variants that the author reports as faster with identical outputs. No concrete merge-blocking risk was found in the supplied context.

Pre-merge checks: Passed 4 · Failed 1

Failed Failed checks: 1 warning

Check name Status Explanation Resolution
Docstring Coverage Warning Docstring coverage is 5.88% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff with cyclomatic complexity of at least 2. Documentat… Write docstrings for the functions missing them to satisfy the coverage threshold.
Passed Passed checks: 4 passed
Check name Status Explanation
Title check Passed The title clearly identifies the performance change, the Cake MXFP8 component, the band-path programs, and the three SM107 entries.
Description check Passed The description is detailed and directly explains the dispatch changes, affected architectures, benchmarks, output compatibility, and package changes. It does not include the template headings for rel…
Linked Issues check Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check Passed Check skipped because no linked issues were found for this pull request.
Full details: Description check

Explanation

The description is detailed and directly explains the dispatch changes, affected architectures, benchmarks, output compatibility, and package changes. It does not include the template headings for related issues, checklist results, or reviewer notes, but the core change description is complete.

Full details: Docstring Coverage

Explanation

Docstring coverage is 5.88% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff with cyclomatic complexity of at least 2. Documentation-only edits and deletions within surviving functions are included; unchanged diff context and fully deleted functions are excluded. Analyzed 51 functions across 7 files. (1 skipped: 1 unsupported.)

Resolution

Write docstrings for the functions missing them to satisfy the coverage threshold.

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@flashinfer-bot run tests/utils/test_cake_gated_act_mxfp8.py tests/utils/test_cake_gated_act_mxfp8_api.py

@yyihuang
yyihuang enabled auto-merge (squash) October 29, 2026 00:21
@yyihuang
yyihuang merged commit 0a99c90 into flashinfer-ai:main Oct 29, 2026
29 of 31 checks passed
yyihuang added a commit that referenced this pull request Oct 29, 2026
…SM103 backward entry (#7880)

The Cake fused SwiGLU + MXFP8 quantization kernel computes silu(gate) *
up from a BF16 input [M, 2K] and quantizes the result to MXFP8. It
stores one E8M0 scale (RCEIL rounding) per 32 E4M3 values, in the
swizzled 128 x 4 layout. The kernel has one data type and six forms. The
forward form is `flashinfer.silu_and_mul_mxfp8_quantize` and the
backward form is `flashinfer.silu_and_mul_mxfp8_quantize_backward`. Each
can write rowwise, colwise or both outputs.
`flashinfer.cake_gated_act_mxfp8_backend` runs one program per call and
picks it by M * K for each architecture. This PR changes program
selection for two backward entries. On sm_100a (B200), backward colwise
with M * K in [2^22, 2^24) now runs the packed-sigmoid form with the
called band path at 10 CTAs per SM. On sm_103a (GB300), backward both
with M * K in [2^24, 3 * 2^24) now runs the two-row form with
L1::no_allocate loads, packed sigmoid and the called band path at 7 CTAs
per SM. The sm_100a entry already uses these settings from 2^24.

The baseline is the previous Cake version of this kernel, which is the
package on FlashInfer main from #7783. With block-scaled inputs the
changed rows are faster: B200 4096 x 2048 backward colwise is 1.112x,
and GB300 4096 x 7168 backward both is 1.030x. With unit-normal inputs,
both changed rows are ties within the run-to-run spread. Every other row
runs the same machine code as before and stays within run-to-run noise.
On B200, the 131072 x 8192 block-scaled rows read 0.996x to 1.014x under
the GPU power cap, with the same program on both sides. That is noise,
not a gain or a loss. With unit-normal inputs, all rows are ties within
the spread: 0.992x to 1.010x on B200 and 0.998x to 1.001x on GB300.

Both versions run in the same process on the same GPU, in 8 alternating
paired rounds, with a cold L2 before every launch. Latency is the mean
over pairs of each sample's median CUPTI kernel time, in microseconds.
Speedup is the previous latency divided by this PR's latency, so a value
above 1 means this PR is faster. Block-scaled inputs are normals with
per-32-block scales spread over a wide exponent range. The GB300 run
used a package with the same machine code as this PR. The package goes
from 72 to 74 per-arch programs across 61 records. One record is new,
and one existing sm_100a record gains sm_103a. The exporter regenerates
the other kernel.cu files, and their machine code is unchanged. Outputs
are byte-identical to the previous version, and the public API is
unchanged.

### NVIDIA B200 (sm_100a, 148 SMs), CUDA 13.4

| M x K | Pass | Unit normals: previous Cake (µs) | This PR (µs) |
Speedup | Block-scaled: previous Cake (µs) | This PR (µs) | Speedup |
|---|---|---:|---:|---:|---:|---:|---:|
| 128 x 128 | fwd rowwise | 2.27 | 2.27 | 1.001x | 2.62 | 2.62 | 1.000x
|
| 128 x 128 | fwd colwise | 2.33 | 2.33 | 0.999x | 2.65 | 2.65 | 1.000x
|
| 128 x 128 | fwd both | 2.46 | 2.46 | 1.000x | 2.80 | 2.79 | 1.001x |
| 128 x 128 | bwd rowwise | 2.43 | 2.42 | 1.000x | 2.64 | 2.64 | 1.000x
|
| 128 x 128 | bwd colwise | 2.54 | 2.54 | 1.000x | 2.68 | 2.68 | 1.000x
|
| 128 x 128 | bwd both | 2.72 | 2.72 | 1.000x | 2.88 | 2.88 | 0.999x |
| 4096 x 2048 | fwd rowwise | 9.76 | 9.76 | 1.000x | 10.00 | 10.00 |
1.000x |
| 4096 x 2048 | fwd colwise | 10.46 | 10.46 | 1.000x | 12.85 | 12.85 |
1.000x |
| 4096 x 2048 | fwd both | 11.66 | 11.66 | 1.000x | 13.68 | 13.67 |
1.000x |
| 4096 x 2048 | bwd rowwise | 14.08 | 14.08 | 1.000x | 14.56 | 14.56 |
1.000x |
| 4096 x 2048 | bwd colwise | 15.02 | 15.02 | 1.000x | 18.54 | 16.67 |
1.112x |
| 4096 x 2048 | bwd both | 18.00 | 18.00 | 1.000x | 19.64 | 19.64 |
1.000x |
| 4096 x 7168 | fwd rowwise | 25.39 | 25.38 | 1.000x | 25.08 | 25.08 |
1.000x |
| 4096 x 7168 | fwd colwise | 26.51 | 26.50 | 1.000x | 31.97 | 31.97 |
1.000x |
| 4096 x 7168 | fwd both | 31.28 | 31.29 | 1.000x | 35.69 | 35.69 |
1.000x |
| 4096 x 7168 | bwd rowwise | 39.41 | 39.41 | 1.000x | 40.55 | 40.56 |
1.000x |
| 4096 x 7168 | bwd colwise | 41.45 | 41.46 | 1.000x | 46.07 | 46.08 |
1.000x |
| 4096 x 7168 | bwd both | 50.57 | 50.57 | 1.000x | 51.91 | 51.91 |
1.000x |
| 16384 x 7168 | fwd rowwise | 90.18 | 90.19 | 1.000x | 89.27 | 89.26 |
1.000x |
| 16384 x 7168 | fwd colwise | 92.21 | 92.22 | 1.000x | 101.59 | 101.54
| 1.001x |
| 16384 x 7168 | fwd both | 108.83 | 108.82 | 1.000x | 122.87 | 122.87 |
1.000x |
| 16384 x 7168 | bwd rowwise | 140.48 | 140.47 | 1.000x | 144.19 |
144.20 | 1.000x |
| 16384 x 7168 | bwd colwise | 144.72 | 144.73 | 1.000x | 159.71 |
159.70 | 1.000x |
| 16384 x 7168 | bwd both | 186.45 | 186.56 | 0.999x | 185.77 | 185.77 |
1.000x |
| 131072 x 8192 | fwd rowwise | 761.64 | 761.01 | 1.001x | 822.26 |
811.22 | 1.014x |
| 131072 x 8192 | fwd colwise | 794.20 | 791.10 | 1.004x | 921.09 |
918.40 | 1.003x |
| 131072 x 8192 | fwd both | 987.24 | 983.91 | 1.003x | 1143.59 |
1148.47 | 0.996x |
| 131072 x 8192 | bwd rowwise | 1219.66 | 1229.47 | 0.992x | 1403.14 |
1393.85 | 1.007x |
| 131072 x 8192 | bwd colwise | 1380.15 | 1370.43 | 1.007x | 1540.72 |
1531.41 | 1.006x |
| 131072 x 8192 | bwd both | 1743.41 | 1725.95 | 1.010x | 1991.55 |
1968.00 | 1.012x |

### NVIDIA GB300 (sm_103a, 152 SMs), CUDA 13.4

| M x K | Pass | Unit normals: previous Cake (µs) | This PR (µs) |
Speedup | Block-scaled: previous Cake (µs) | This PR (µs) | Speedup |
|---|---|---:|---:|---:|---:|---:|---:|
| 128 x 128 | fwd rowwise | 1.99 | 2.00 | 0.998x | 2.29 | 2.29 | 1.001x
|
| 128 x 128 | fwd colwise | 2.06 | 2.06 | 1.000x | 2.36 | 2.36 | 1.000x
|
| 128 x 128 | fwd both | 2.16 | 2.16 | 1.000x | 2.46 | 2.46 | 1.000x |
| 128 x 128 | bwd rowwise | 2.13 | 2.13 | 1.001x | 2.23 | 2.23 | 0.999x
|
| 128 x 128 | bwd colwise | 2.27 | 2.27 | 0.998x | 2.42 | 2.42 | 0.999x
|
| 128 x 128 | bwd both | 2.40 | 2.40 | 0.998x | 2.56 | 2.56 | 1.000x |
| 4096 x 2048 | fwd rowwise | 9.04 | 9.04 | 1.000x | 9.51 | 9.51 |
1.000x |
| 4096 x 2048 | fwd colwise | 9.71 | 9.71 | 1.000x | 12.36 | 12.35 |
1.000x |
| 4096 x 2048 | fwd both | 10.99 | 10.98 | 1.000x | 13.31 | 13.30 |
1.001x |
| 4096 x 2048 | bwd rowwise | 13.49 | 13.48 | 1.001x | 13.80 | 13.80 |
1.000x |
| 4096 x 2048 | bwd colwise | 14.19 | 14.19 | 1.000x | 17.15 | 17.16 |
1.000x |
| 4096 x 2048 | bwd both | 16.97 | 16.97 | 1.000x | 19.25 | 19.25 |
1.000x |
| 4096 x 7168 | fwd rowwise | 24.04 | 24.03 | 1.000x | 25.06 | 25.07 |
1.000x |
| 4096 x 7168 | fwd colwise | 25.37 | 25.37 | 1.000x | 29.32 | 29.33 |
1.000x |
| 4096 x 7168 | fwd both | 29.97 | 29.97 | 1.000x | 34.68 | 34.68 |
1.000x |
| 4096 x 7168 | bwd rowwise | 37.91 | 37.91 | 1.000x | 39.65 | 39.65 |
1.000x |
| 4096 x 7168 | bwd colwise | 39.67 | 39.68 | 1.000x | 43.26 | 43.26 |
1.000x |
| 4096 x 7168 | bwd both | 47.84 | 47.80 | 1.001x | 50.10 | 48.65 |
1.030x |
| 16384 x 7168 | fwd rowwise | 86.77 | 86.80 | 1.000x | 90.66 | 90.66 |
1.000x |
| 16384 x 7168 | fwd colwise | 90.03 | 90.00 | 1.000x | 96.05 | 96.04 |
1.000x |
| 16384 x 7168 | fwd both | 104.99 | 104.94 | 1.000x | 113.59 | 113.59 |
1.000x |
| 16384 x 7168 | bwd rowwise | 135.37 | 135.37 | 1.000x | 139.17 |
139.16 | 1.000x |
| 16384 x 7168 | bwd colwise | 139.23 | 139.23 | 1.000x | 148.32 |
148.31 | 1.000x |
| 16384 x 7168 | bwd both | 175.40 | 175.43 | 1.000x | 176.95 | 176.97 |
1.000x |
| 131072 x 8192 | fwd rowwise | 738.02 | 738.06 | 1.000x | 755.48 |
755.40 | 1.000x |
| 131072 x 8192 | fwd colwise | 756.59 | 756.59 | 1.000x | 816.21 |
816.21 | 1.000x |
| 131072 x 8192 | fwd both | 906.47 | 906.42 | 1.000x | 954.61 | 954.76
| 1.000x |
| 131072 x 8192 | bwd rowwise | 1170.76 | 1170.73 | 1.000x | 1203.50 |
1203.53 | 1.000x |
| 131072 x 8192 | bwd colwise | 1220.39 | 1220.37 | 1.000x | 1293.39 |
1293.41 | 1.000x |
| 131072 x 8192 | bwd both | 1563.22 | 1563.39 | 1.000x | 1559.46 |
1559.47 | 1.000x |

Cake has no other variants of this kernel beyond these six BF16-to-MXFP8
forms with the swizzled scale layout, and the family ships on sm_100a
(B200), sm_103a (GB300) and sm_107a (R200).


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-->

<!-- coderabbit-ai-generated:v1 -->

## Summary by CodeRabbit

* **New Features**
* Added MXFP8 gated-activation kernel support for additional GPU
architectures, including `sm_100a` and `sm_103a`.
* Expanded kernel selection for backward operations across supported
architectures and workload sizes.
* **Refactor**
* Updated internal kernel implementations without changing their
existing calculations or output behavior.

<!-- end of auto-generated comment: release notes by coderabbit.ai -->

Co-authored-by: Yingyi Huang <averyh@nvidia.com>
Co-authored-by: Claude <noreply@anthropic.com>
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