bench(cake_mla_varq_dcp_decode): drop the package README and add a query-pattern benchmark option (second-round attribution, no module change) by yyihuang · Pull Request #5588 · flashinfer-ai/flashinfer

yyihuang · 2026-09-27T04:32:55Z

Developed by the CAKE team, the kernels in this PR outperform the relevant SOTA baselines at the time of merge on the vast majority of performance benchmark shapes, matching them otherwise.

Developed by the CAKE team, the existing kernels evaluated in this PR outperform the relevant SOTA baseline on all 24 reported performance shapes on B200 and GB300. This PR changes benchmark coverage and documentation only.

Summary

Second optimisation round on flashinfer.experimental.cake_mla_varq_dcp_decode (the Blackwell MLA variable-query decode with static decode context parallelism from #5577). Six levers were measured on B200 and GB300 against the shipped kernel with same-tree A/B runs and timeline stamps; none beat it, so the generated modules and the host plan are unchanged. This PR carries the two package-side follow-ups:

benchmarks/bench_cake_mla_varq_dcp_decode.py: --q-pattern {row,uniform,ragged} overrides every row's query-length pattern (default: the row's own), which reproduces the round's main finding on the split rows (below).
flashinfer/experimental/cake_mla_varq_dcp_decode/README.md is removed; the package is documented by its module docstrings, the test module (validated shape set, replay spread) and the benchmark. The three references to it (flashinfer/mla/_core.py docstring, the test's replay-spread docstring, the benchmark help text) are reworded.

No CUDA, planner or runner change; the validated tolerances, the prepared-runner replay footprint and the 38-row contract are those of #5577.

What was measured

Same-tree A/B (candidate vs shipped trace, alternating arms, three repeats per row, cold-L2 CUPTI timing) on both GPUs:

lever	change	result
start-up	extra clusters issue their Q / K loads before publishing the unit token	fp8 h128 w8 b16 q1 s32k -5 % (B200) / -6 % (GB300): the load warp blocks in the TMA issue queue and the token waits
start-up	partition-pass loads hoisted to kernel entry	geomean -1 % on both GPUs
epilogue	two-round pipelined O epilogue (TMEM loads of round i+1 in flight while round i converts and stores)	GB300 within noise on re-measure, B200 FP8 rows -1..-4 %
split rows	in-kernel last-arriver merge replacing the reduce kernel	-4..-9 % on every split row on both GPUs (one cluster folds every partial of an item through one SM pair's L2 path; the reduce kernel spreads an item over eight CTAs and overlaps through PDL)
teardown	launch / empty-geometry / one-tile floor probes	2.4-3.2 us from the last store to the kernel end in every geometry; a trivial kernel needs 1.25-1.30 us for launch + exit; nothing runs after the last store
host plan	`unit_min` 2 / 4 / 8; static unit size sweeps	`unit_min` neutral; smaller static units gain 4-13 % on the ragged-query `mtp3` rows but lose 5-9 % on the same geometry with uniform query lengths (`--q-pattern uniform`), which the host plan cannot distinguish from host-known scalars

Roofline: every row at 14-57 % of the HBM / dense-tensor roofline on both GPUs; the tightest row (fp8_h128_w8_b16_q1_s32k, 18.6 / 20.1 us) is fixed-cost bound: Q and first K tile land at 3.4-3.5 us on a flushed L2, first QK MMA at 3.9 / 4.4 us, epilogue 1.5-1.7 us per unit, merge 0.6 us, teardown 2.4-3.2 us.

Shipped-kernel performance (same-session paired timing, cute_dsl_mla_decode / this route): GB300 geomean 1.196, B200 1.195, 24 / 24 rows above 1 on both. The export-protocol tables of #5577 remain the published numbers (geomean 1.1817 / 1.1791, 24 / 24).

Baselines and their source PRs

Route under test: flashinfer.experimental.cake_mla_varq_dcp_decode as merged by feat(cake_mla_varq_dcp_decode): Cake MLA variable-query decode with DCP for SM100 / SM103 #5577 (f89d15f2c, 2026-09-27): cake_backend.py, cake_jit.py, csrc/cake_mla_varq_dcp_decode/{sm_100a,sm_103a}/*.cu. Unchanged by this PR.
Baseline: upstream CuTe-DSL cute_dsl_mla_decode(..., is_var_seq=True, enable_dcp=True, cum_seq_lens_q, max_q_len, causal_seqlens_kv_global) from feat(mla): support variable-Q decode with DCP in CuTeDSL #4719 (flashinfer/cute_dsl/attention/monolithic/mla_decode_fp16.py, mla_decode_fp8.py); no change to these files between feat(cake_mla_varq_dcp_decode): Cake MLA variable-query decode with DCP for SM100 / SM103 #5577's merge base and this branch's base (7d9679390).
Test oracle: tests/experimental/test_cake_mla_varq_dcp_decode.py from feat(cake_mla_varq_dcp_decode): Cake MLA variable-query decode with DCP for SM100 / SM103 #5577 (FP32 global-coordinate reference, upstream DCP test semantics).

Benchmark commands

python benchmarks/bench_cake_mla_varq_dcp_decode.py
python benchmarks/bench_cake_mla_varq_dcp_decode.py --q-pattern uniform --rows perf_bf16_h96_w8_b32_mtp3_s32k perf_fp8_h48_w4_b32_mtp3_s32k
python -m pytest tests/experimental/test_cake_mla_varq_dcp_decode.py -q

Pre-commit (upstream hooks, pinned ruff 0.12.8 / mypy 1.17.1) clean on the touched files.

🤖 Generated with Claude Code

Summary by CodeRabbit

New Features
- Benchmark runs can use uniform or ragged query-length patterns in addition to the default row pattern. The selected pattern appears in output labels.
Documentation
- API guidance now points to tests and benchmarks for validated shapes and comparisons.
- Replay accuracy notes clarify expected output differences for split requests and reproducibility for unsplit rows.

References

The shared reference corpus for CAKE kernel development includes the following projects, documentation, and existing CAKE work:

GPU programming and instructions: NVIDIA CUDA Programming Guide, NVIDIA PTX ISA, and gau-nernst's tcgen05 tutorial and CUDA kernel examples.
Kernel programming libraries and compilers: NVIDIA CUTLASS / CuTe, Triton, TileLang, NVIDIA cuTile Python, and ThunderKittens (ThunderKittens 2.0 techniques).
Attention and inference: FlashAttention (including Hopper and CuTe implementations), FlashInfer, including its TRT-LLM kernel integration, Flash Linear Attention, SageAttention, FlashAttention-FP4, and FastVideo.
GEMM and MoE: DeepGEMM, SonicMoE, Alpha-MoE, and Mixture of Kittens.
Clustering and nearest-neighbor kernels: Flash K-Means and FlashLib.
Existing CAKE implementations and PRs: CAKE-generated kernel progress tracker and PR index (#4254).

These are corpus-level references. PR-specific implementation details, changes, and benchmark references are documented above.

…nd add a query-pattern benchmark option No kernel or host-plan change: the second optimisation round measured six levers on B200 and GB300 and adopted none. The package README records where the time goes (roofline share, fixed costs of the tightest row, rejected changes with numbers) and why the static unit size stays at the uniform-query optimum. The benchmark gains --q-pattern {row,uniform,ragged} so the ragged-versus-uniform query-length effect on the split rows can be reproduced. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

yyihuang · 2026-09-27T04:33:19Z

/bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

yyihuang · 2026-09-27T04:33:20Z

@flashinfer-bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

coderabbitai · 2026-09-27T04:33:29Z

Navigate logical layers of code changes, visualize relationships, and explore their blast radius.

📝 Walkthrough

Walkthrough

The benchmark adds an option to select query-length patterns across rows. The experimental API README is removed, the API docstring now points to tests and a benchmark, and the replay-tolerance description is updated.

Changes

Query Pattern Benchmarking

Layer / File(s)	Summary
Query pattern selection `benchmarks/bench_cake_mla_varq_dcp_decode.py`	The benchmark accepts `row`, `uniform`, or `ragged` through `--q-pattern`. The default preserves each row’s configured pattern. Other selections replace each row’s pattern and add a suffix to the output label.
API reference and validation description `flashinfer/experimental/cake_mla_varq_dcp_decode/README.md`, `flashinfer/mla/_core.py`, `tests/experimental/test_cake_mla_varq_dcp_decode.py`	The experimental README is deleted. The API docstring now points to the tests and comparison benchmark. The replay-tolerance docstring specifies approximate output variation for split requests and retains the stated `lse` spread and unsplit-row reproducibility.

Priority: ⬇️ Low

Estimated code review effort: 2 (Simple) | ~10 minutes

Change: Feature

Merge Risk: 🔵 Low · up to f1f20

The benchmark patterns behave as documented. Tighten the replay check if the approximately 5e-4 bound is relied on, since current tests permit larger drift; no runtime regression is established.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 66.67% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 3 functions across 3 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Title check	✅ Passed	The title clearly identifies both primary changes: removing the package README and adding the query-pattern benchmark option. It is longer than necessary but remains specific and relevant.
Description check	✅ Passed	The description is comprehensive and on-topic. It explains the optimization study, documents the benchmark option, records measured results and baselines, lists validation commands, and reports pre-co…

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flashinfer-bot · 2026-09-27T04:33:32Z

GitLab MR !1726 has been created, and the CI pipeline #70020217 is currently running. I'll report back once the pipeline job completes.

flashinfer-bot · 2026-09-27T05:09:56Z

[FAILED] Pipeline #70020217 — 24/25 executed test jobs passed

Compared with nightly #69913127.

Unit Tests

GPU	CUDA 12.9	CUDA 13.0	CUDA 13.4	Notes
B200	✅ Pass	✅ Pass	✅ Pass	—
GB200	✅ Pass	✅ Pass	✅ Pass	—
GB300	✅ Pass	✅ Pass	✅ Pass	—
H100	✅ Pass	✅ Pass	✅ Pass	—
RTX Pro 6000 Blackwell	✅ Pass	✅ Pass	✅ Pass	—
VR200	—	—	✅ Pass	—

✅ Pass · 🟡 Old failure · ❌ New failure · ⏱ Test timeout · ⚠️ Infrastructure · ❔ Unknown or unclassified · — Not run

Multi-GPU and Multi-Node Tests — 5/6 passed

GPU	CUDA 12.9	CUDA 13.0	CUDA 13.4	Notes
B300 (multi-GPU)	✅ Pass	❔ Unknown	—	—
GB200 (multi-node)	✅ Pass	✅ Pass	—	—
GB300 (multi-node)	✅ Pass	✅ Pass	—	—

No individual test or infrastructure failures could be extracted.

yyihuang · 2026-09-27T05:12:01Z

Pipeline #70020217: 24/25 test jobs passed; every unit-test job (B200 / GB200 / GB300 / H100 / RTX Pro 6000 / VR200, CUDA 12.9 / 13.0 / 13.4) is green. The one failed job is multi_gpu_test_b300 [cu130], where tests/attention/test_parallel_attention.py::test_attn_parallel aborted on local rank 2 (exitcode -6); this PR changes only the package README and a benchmark option and does not touch that test path. Re-triggering.

yyihuang · 2026-09-27T05:12:02Z

/bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

yyihuang · 2026-09-27T05:12:03Z

@flashinfer-bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

flashinfer-bot · 2026-09-27T05:13:01Z

GitLab MR !1726 has been created, and the CI pipeline #70024349 is currently running. I'll report back once the pipeline job completes.

yyihuang · 2026-09-27T05:33:52Z

/bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

yyihuang · 2026-09-27T05:33:53Z

@flashinfer-bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

…cstrings at the test and benchmark modules The package is documented by its module docstrings, the test module (validated shape set, replay spread) and the benchmark; the second-round attribution lives in the Cake design record. The three references to the README are reworded. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

flashinfer-bot · 2026-09-27T05:34:25Z

GitLab MR !1726 has been updated with latest changes, and the CI pipeline #70026353 is currently running. I'll report back once the pipeline job completes.

yyihuang · 2026-09-27T05:34:38Z

/bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

yyihuang · 2026-09-27T05:34:39Z

@flashinfer-bot run tests/experimental/test_cake_mla_varq_dcp_decode.py

flashinfer-bot · 2026-09-27T05:35:30Z

GitLab MR !1726 has been created, and the CI pipeline #70026778 is currently running. I'll report back once the pipeline job completes.

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🧹 Nitpick comments (1)

tests/experimental/test_cake_mla_varq_dcp_decode.py (1)
485-486: 🎯 Functional Correctness | 🔵 Trivial | ⚡ Quick win

Enforce the documented absolute out spread.

_assert_replay_close uses atol=1e-3 and rtol=2**-7, so both reachable replay tests can accept an out difference greater than the newly documented 5e-4 absolute spread. Use a pure absolute tolerance for this assertion.
Suggested fix
-    torch.testing.assert_close(out.float(), other_out.float(), atol=1e-3, rtol=2.0**-7)
+    torch.testing.assert_close(out.float(), other_out.float(), atol=5e-4, rtol=0)
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In @tests/experimental/test_cake_mla_varq_dcp_decode.py around lines 485 - 486,
Update _assert_replay_close to enforce the documented absolute out spread by
using an absolute tolerance of 5e-4 and zero relative tolerance for the out
comparison; leave the lse assertion unchanged.

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Nitpick comments:
In @tests/experimental/test_cake_mla_varq_dcp_decode.py:
- Around line 485-486: Update _assert_replay_close to enforce the documented
absolute out spread by using an absolute tolerance of 5e-4 and zero relative
tolerance for the out comparison; leave the lse assertion unchanged.

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flashinfer-bot · 2026-09-27T06:51:21Z

[SUCCESS] Pipeline #70026778: 25/25 executed test jobs passed

…r52 kernel (deferred O rescale, wider long-request threshold) (#5602) ## Summary Regenerates the Cake-generated `backend="cake"` Kimi-K3 MLA FP8 paged attention route (#5552; v9, r50 and r51 programs in the previous heads of this PR) for the **r52 kernel** on SM100 (B200) and SM103 (B300 / GB300). The host side is unchanged from the r51 head (same planner, grids and kernel arguments), so this head only moves the generated programs of both architectures; every file is written by the exporter from the same producer tree. What r52 changes against the r51 programs (`33b85998c`): - **Deferred O rescale (wide kernel).** When a row's lazy E4M3 reference moves at tile t, the softmax warps used to wait for PV(t-1) to retire and rescale their O lanes in TMEM (four 64-column `tcgen05.ld` / `tcgen05.st` round trips per warp) *before* storing P(t), so every move stalled the P publish by 3-4 us and, with the latent K stages held until PV(t), the load ring behind it. The warps now store P(t) and arrive `p_full` first, then wait for PV(t-1), rescale and arrive a new `o_ready` mbarrier (tile parity, 4 warps x 2 CTAs, arrived every tile); the MMA warp waits `o_ready(t)` with `p_full(t)` before PV(t). Outputs are unchanged (same FP32-reference max_abs on every checked row). - **Wider long-request threshold.** Requests with at least 32768 cached tokens publish their reference 4 (was 2) octaves above the running max, so a move needs a 6-octave (was 4) jump. On the contract inputs (peaked profile, one dominant key per row) this cuts the reference moves from 12.65 to 4.1 per mtp_h96_b8_q4 cluster lifetime (8.1 -> 1.5 on the H96 batch-8 decode rows) for the same speed a 7-octave threshold gives on that row. FP32-reference max_abs over all 25 contract rows stays inside 0.01 / 0.02 with zero mismatches (prefill_h96_b1_q2048_kv131072 0.0029 -> 0.0059 over 100.7 M elements, prefill_h96_b2 0.0068 -> 0.0088, mtp_h96_b8_q4 0.0012 -> 0.0020); a 7-octave threshold failed that first row (57 mismatches) and was rejected. Short-KV rows are unchanged. - Both levers measured on B300 against the r51 tree (main kernel, 3 alternating rounds, CUDA-graph cold-L2): mirror_h96_b8 0.994, mtp_h96_b8_q2 0.987, mtp_h96_b8_q4 0.985, prefill_h96_b2 0.981 (removing the rescale path entirely: 0.987 / 0.982 / 0.986 / 0.978). ## Performance (same-session CUPTI cold-L2, CUDA-graph replay, 3 alternating rounds; Cake vs the fastest existing FlashInfer route) | row | route | B200 Cake us (median of 3) | B200 vs best FI | B300 Cake us (median of 3) | B300 vs best FI | |---|---|---:|---:|---:|---:| | trace_h12_b1_q1_kv76800 | row tiles | 21.1 | **1.173x** | 20.8 | **1.132x** | | trace_h12_b2_q1_kv77699 | row tiles | 29.2 | **1.060x** | 29.1 | **1.052x** | | trace_h12_b3_q1_kv261120 | row tiles | 89.7 | **1.043x** | 90.6 | **1.026x** | | trace_h12_b4_q1_kv268800 | row tiles | 112.8 | **1.096x** | 113.5 | **1.058x** | | trace_h12_b5_q1_kv276480 | row tiles | 138.4 | **1.075x** | 139.9 | **1.070x** | | trace_h12_b6_q1_kv467751 | row tiles | 254.3 | **1.073x** | 256.5 | **1.067x** | | trace_h12_b7_q1_kv299613 | row tiles | 195.5 | **1.068x** | 197.8 | **1.066x** | | trace_h12_b8_q1_kv342305 | row tiles | 246.8 | **1.078x** | 248.5 | **1.073x** | | trace_h12_b9_q1_kv348705 | row tiles | 279.2 | **1.075x** | 280.3 | **1.070x** | | trace_h12_b10_q1_kv474166 | row tiles | 412.8 | **1.088x** | 411.8 | **1.075x** | | trace_h12_b11_q1_kv474405 | row tiles | 453.3 | **1.076x** | 450.6 | **1.069x** | | mirror_h96_b1_q1_kv76800 | wide | 23.7 | **1.159x** | 23.1 | **1.130x** | | mirror_h96_b2_q1_kv77699 | wide | 33.3 | **1.022x** | 33.1 | **1.021x** | | mirror_h96_b6_q1_kv467751 | wide | 331.2 | **1.033x** | 320.4 | **1.063x** | | mirror_h96_b7_q1_kv299613 | wide | 247.3 | **1.043x** | 239.6 | **1.049x** | | mirror_h96_b8_q1_kv342305 | wide | 318.3 | **1.052x** | 309.5 | **1.058x** | | mtp_h12_b8_q2_kv342305 | row tiles | 256.7 | **1.227x** | 253.0 | **1.220x** | | mtp_h12_b8_q4_kv342305 | row tiles | 278.4 | **1.148x** | 263.6 | **1.190x** | | mtp_h12_b8_q8_kv342305 | wide | 321.2 | **1.047x** | 313.3 | **1.049x** | | mtp_h96_b8_q2_kv342305 | wide | 616.2 | **1.126x** | 607.5 | **1.038x** | | mtp_h96_b8_q4_kv342305 | wide | 946.2 | **1.046x** | 902.6 | **1.027x** | | mtp_h96_b8_q8_kv342305 | wide | 1782.4 | **1.223x** | 1776.7 | **1.131x** | | prefill_h12_b1_q2048_kv131072 | wide | 2531.1 | **1.070x** | 2534.7 | **1.033x** | | prefill_h12_b2_q512_kv32768 | wide | 327.5 | **1.200x** | 327.9 | **1.135x** | | prefill_h12_b4_q1024_kv8192 | wide | 331.6 | **1.091x** | 321.2 | **1.120x** | | prefill_h96_b1_q2048_kv131072 | wide | 20226.7 | **1.042x** | 20314.9 | **1.028x** | | prefill_h96_b2_q512_kv32768 | wide | 2560.0 | **1.039x** | 2490.9 | **1.051x** | `vs best FI` = median over the 3 rounds of (fastest of `auto` / `trtllm-gen` / `cute-dsl` divided by Cake) in that round (>1 = Cake faster); `Cake us` = median of the 3 rounds; same session and GPU (B200 `nsc-svg-slurm-1-gpu-157`, 148 SMs, allocation 2076841, step `eb75a751`; B300 `pool0-0048 (B300 SXM6 AC)`, 148 SMs, allocation 583080, step `2ed26b9c`). `route` is the schedule the planner selects for the row. **The route is faster than every existing FlashInfer backend on all 27 rows on both GPUs: the user's rule (every shape > 1 vs every baseline) is met on B200 and on B300.** There are no misses. The closest rows are mirror_h96_b2 (1.022x on B200, 1.021x on B300) and, on B300, trace_h12_b3 (1.026x) and the previous round's miss mtp_h96_b8_q4 (1.027x `auto` / 1.029x `cute-dsl`; 1.046x on B200). Against the r51 head of this PR, the r52 tree is 0.969x time (gpu-157 vs the r51d gate on the same node) (B200) / 0.987x time (pool0-0048 vs the r51d gate node pool0-0275) (B300) of the r51d gate time over the 27 rows (geomean; Against the r51d gate benches the H96 wide rows take 0.92-0.98x of their previous time on B200 (mirror_h96_b8 0.919x, mtp_h96_b8_q2 0.930x, mtp_h96_b8_q4 0.953x, prefill_h96_b2 0.964x) and 0.94-0.99x on B300 (mtp_h96_b8_q4 0.939x, prefill_h96_b2 0.955x, mtp_h96_b8_q8 0.957x, mirror_h96_b8 0.975x); the H12 rows are unchanged within noise (same kernels). The B200 comparison is same-node, different session; the same-node paired A/B behind the design numbers is on B300 pool0-0143 (section r52).). ## Baselines and their source PRs The `vs best FI` column compares against the two existing FlashInfer routes of the same public entry points, resolved at this branch's upstream merge-base `7b8f6129c` (2026-09-27, #5585): - **trtllm-gen** (`backend="trtllm-gen"`, also what `backend="auto"` selects for H12): `trtllm_batch_decode_with_kv_cache_mla` / `trtllm_prefill_with_kv_cache_mla` in `flashinfer/mla/_core.py` launching the prebuilt TRT-LLM-gen FMHA cubins pinned in `flashinfer/artifacts.py` (`TRTLLM_GEN_FMHA = 2d6a5a02…/fmha/trtllm-gen/`; pin set by #4654 `857bc3a11`, 2026-08-26). Test oracle: `tests/attention/test_trtllm_gen_mla.py`. - **cute-dsl** (`backend="cute-dsl"`, what `auto` selects for H96): the CuTe-DSL MLA decode family under `flashinfer/cute_dsl/attention/` — `mla_decode_fp8.py`, `mla_config.py`, `wrappers/batch_mla.py` (#2805, `00ac5053d`, 2026-04-13; H64/H96 configs #3235 `2d0e0efac` 2026-05-11; SM107 reland #4280 `5b1af9724` 2026-07-30), `mla_dispatch.py` + `monolithic/mla_decode.py` (#3296 `e91ac8f15` 2026-05-21; LSE base semantics #4650 `d7a7447cb` 2026-09-21), reached through `flashinfer/mla/_core.py` (cute-dsl MLA op #2743 `31b63bc3d` 2026-03-27). Test oracle: `tests/attention/test_trtllm_gen_mla.py` / the CuTe-DSL MLA tests of those PRs. Since the previous merge-base `bf82326b0` (the #5552 comparison) no upstream commit touched the `cute-dsl` MLA kernels (`git log bf82326..7b8f612 -- flashinfer/cute_dsl/attention` is empty), the `TRTLLM_GEN_FMHA` pin is unchanged (#5149 `e34a1735a` moved only the `batched_gemm` artifact in `flashinfer/artifacts.py`), and `flashinfer/mla/_core.py` changed only by the `backend="cake"` dispatch additions of #5552, #5577 and #5588. The Cake route in this PR is compared against exactly those implementations. ## Unsupported (rejected explicitly) Unchanged from #5552: sparse top-k MLA, attention sinks, LSE output, DCP, skip-softmax, FP16 softmax, PDL as a caller option (`enable_pdl`: the attention kernel is an ordinary launch on the caller's stream; internally the route launches its split-KV merge as a programmatic dependent of the attention kernel), NVFP4 / uint8 caches, `multi_ctas_kv_counter_buffer`. Requests with > 64 packed rows whose longest KV is below 8192 tokens run the 96-row tiles (the wide kernel's lazy-E4M3 reference needs atol 0.012 at KV 4096 against the 0.01 gate). ## Tests - `tests/mla/test_cake_kimi_k3_mla.py` (30 cases: decode H12/H96 incl. the long-KV wide-route set, MTP variable-Q (incl. the 60-row RT=64 case and a wide-route H96 case), incremental prefill with prefix reuse and the wide-route prefill at 0.01 / 0.02, route selection with the 8192 threshold, CUDA-graph replay with a changed page table on both routes, unsupported-option rejection, nine host-only wide-split-planner cases and the three tail-plan cases): **30 passed on B200, 30 passed on B300** on the generated programs of this PR head. Upstream pre-commit hooks (mypy, ruff check, ruff format) pass on the hand-written files (the only hook output is the `ruff format` re-wrap already applied as `43cb25a50`). - `tests/attention/test_trtllm_gen_mla.py -k trtllm_mla_blackwell` (dispatch regression for the #4557 route): 18 passed on B200; 12 passed, 6 skipped on B300. - Export receipts (source-vs-generated host-plan + bitwise output parity and ABBA CUPTI timing gates; denominator = 27 perf rows + the two coverage rows, per arch): B200 27 / 29 rows pass (25 perf + 2 coverage rows; source/export geomean 1.0010, perf rows 1.0012); B300 27 / 29 rows pass (25 perf + 2 coverage rows; source/export geomean 1.0013, perf rows 1.0015). Two rows per GPU are refused, both by measurement-validity gates rather than by parity or correctness: `prefill_h96_b1_q2048_kv131072`, the exporter's loaded-SM-clock gate (1312 / 1965 MHz on B200, 1185 / 2032 MHz on B300, below the 0.70 fraction under the sustained power cap; the same row and gate as r50 and r51), and `mirror_h96_b1_q1_kv76800`, whose paired ABBA timing shows a ~1.3 % first-arm advantage on both GPUs (`directional_disagreement` 0.0263 / 0.0204 against a 0.02 limit; source and generated program are the same kernel, bitwise parity holds, source/export 1.0026 / 1.0097). A closed-prior retry round re-measured only these two rows and reproduced both refusals (0.0253 / 0.0218), so they are disclosed rather than re-rolled; the row's speed against the baselines is the gate bench's 1.159x / 1.130x. the B200 and B300 exporter runs generated byte-identical program files (42 files under `csrc/cake_kimi_k3_mla/{sm_100a,sm_103a}` + README + jit registry, per-file SHA-256 equal; the two tarballs differ only in archive metadata). <details><summary>Export receipts (29 rows per architecture, source vs generated: same-session ABBA CUPTI cold-L2 medians, CUDA-graph replay)</summary> | row | route | sm_100a source us | sm_100a export us | sm_100a src/exp | sm_100a verdict | sm_103a source us | sm_103a export us | sm_103a src/exp | sm_103a verdict | |---|---|---:|---:|---:|---|---:|---:|---:|---| | mtp_h12_fixed_q5 | rt64_reduce_w2_sm_100a | 300.6 | 300.5 | 1.0001 | PASS | 268.5 | 268.5 | 1.0001 | PASS | | mtp_h96_fixed_q8_kv8000 | rt96_reduce_w1_sm_100a | 139.6 | 139.8 | 0.9982 | PASS | 125.3 | 125.7 | 0.9967 | PASS | | trace_h12_b1_q1_kv76800 | rt16_reduce_cta_sm_100a | 21.5 | 21.2 | 1.0151 | PASS | 21.2 | 20.9 | 1.0138 | PASS | | trace_h12_b2_q1_kv77699 | rt16_reduce_cta_sm_100a | 29.3 | 29.4 | 0.9967 | PASS | 28.9 | 29.1 | 0.9945 | PASS | | trace_h12_b3_q1_kv261120 | rt16_reduce_cta_sm_100a | 89.6 | 89.7 | 0.9986 | PASS | 90.2 | 90.5 | 0.9968 | PASS | | trace_h12_b4_q1_kv268800 | rt16_reduce_cta_sm_100a | 112.8 | 112.7 | 1.0009 | PASS | 114.0 | 113.9 | 1.0011 | PASS | | trace_h12_b5_q1_kv276480 | rt16_reduce_w4_sm_100a | 138.9 | 139.2 | 0.9975 | PASS | 139.8 | 140.2 | 0.9973 | PASS | | trace_h12_b6_q1_kv467751 | rt16_reduce_w4_sm_100a | 253.5 | 253.7 | 0.9994 | PASS | 253.6 | 253.7 | 0.9995 | PASS | | trace_h12_b7_q1_kv299613 | rt16_reduce_w4_sm_100a | 196.1 | 195.8 | 1.0011 | PASS | 197.3 | 197.3 | 1.0002 | PASS | | trace_h12_b8_q1_kv342305 | rt16_reduce_w4_sm_100a | 249.0 | 249.0 | 0.9999 | PASS | 248.5 | 248.5 | 1.0001 | PASS | | trace_h12_b9_q1_kv348705 | rt16_reduce_w4_sm_100a | 280.9 | 281.2 | 0.9986 | PASS | 279.7 | 280.0 | 0.9990 | PASS | | trace_h12_b10_q1_kv474166 | rt16_reduce_w4_sm_100a | 421.9 | 422.2 | 0.9991 | PASS | 412.5 | 412.8 | 0.9994 | PASS | | trace_h12_b11_q1_kv474405 | rt16_reduce_w4_sm_100a | 463.8 | 463.9 | 0.9997 | PASS | 448.5 | 448.5 | 0.9999 | PASS | | mirror_h96_b1_q1_kv76800 | wide_reduce_cta_sm_100a | — | — | — | FAIL: failed gates: directional_disagreement | — | — | — | FAIL: failed gates: directional_disagreement | | mirror_h96_b2_q1_kv77699 | wide_reduce_cta_sm_100a | 33.3 | 32.9 | 1.0126 | PASS | 33.6 | 32.9 | 1.0194 | PASS | | mirror_h96_b6_q1_kv467751 | wide_reduce_w2_sm_100a | 341.9 | 341.4 | 1.0015 | PASS | 328.5 | 327.9 | 1.0017 | PASS | | mirror_h96_b7_q1_kv299613 | wide_reduce_w2_sm_100a | 257.9 | 257.6 | 1.0014 | PASS | 242.0 | 241.7 | 1.0012 | PASS | | mirror_h96_b8_q1_kv342305 | wide_reduce_w2_sm_100a | 334.0 | 333.6 | 1.0011 | PASS | 320.7 | 320.3 | 1.0014 | PASS | | mtp_h12_b8_q2_kv342305 | rt32_reduce_w4_sm_100a | 261.4 | 261.7 | 0.9987 | PASS | 253.4 | 253.7 | 0.9990 | PASS | | mtp_h12_b8_q4_kv342305 | rt48_reduce_w2_sm_100a | 287.6 | 287.8 | 0.9993 | PASS | 263.9 | 264.1 | 0.9995 | PASS | | mtp_h12_b8_q8_kv342305 | wide_reduce_w2_sm_100a | 334.0 | 333.7 | 1.0009 | PASS | 320.5 | 320.0 | 1.0014 | PASS | | mtp_h96_b8_q2_kv342305 | wide_reduce_w1_sm_100a | 641.3 | 640.7 | 1.0009 | PASS | 619.6 | 619.1 | 1.0008 | PASS | | mtp_h96_b8_q4_kv342305 | wide_reduce_w1_sm_100a | 954.5 | 953.5 | 1.0010 | PASS | 923.8 | 923.2 | 1.0006 | PASS | | mtp_h96_b8_q8_kv342305 | wide_reduce_w1_sm_100a | 1838.8 | 1838.3 | 1.0003 | PASS | 1802.6 | 1802.2 | 1.0002 | PASS | | prefill_h12_b1_q2048_kv131072 | wide_reduce_w1_sm_100a | 2576.4 | 2576.0 | 1.0001 | PASS | 2526.6 | 2525.9 | 1.0003 | PASS | | prefill_h12_b2_q512_kv32768 | wide_reduce_w1_sm_100a | 332.6 | 332.0 | 1.0017 | PASS | 327.7 | 327.3 | 1.0014 | PASS | | prefill_h12_b4_q1024_kv8192 | wide_reduce_w1_sm_100a | 335.8 | 335.1 | 1.0021 | PASS | 316.4 | 315.8 | 1.0020 | PASS | | prefill_h96_b1_q2048_kv131072 | wide_reduce_w1_sm_100a | — | — | — | FAIL: InterleavedTimingError: reportable loaded SM clock 1297/1965 MHz is below the 0.700000 fraction | — | — | — | FAIL: InterleavedTimingError: reportable loaded SM clock 1177/2032 MHz is below the 0.700000 fraction | | prefill_h96_b2_q512_kv32768 | wide_reduce_w1_sm_100a | 2570.3 | 2569.7 | 1.0003 | PASS | 2529.9 | 2529.2 | 1.0003 | PASS | </details> ## Baselines-free numerics evidence carried over from the kernel rounds Every route was measured against the FP32 reference: the routed kernel passes all functional rows at 0.01 / 0.02 on both GPUs (forced-wide, routed and forced-tail plans, 8 rows each); the 20 unchecked perf rows pass on both (20 / 20 (max_abs 0.00586, prefill_h96_b1; 0 mismatches) B200, 20 / 20 (max_abs 0.00586, prefill_h96_b1; 0 mismatches) B300). The deferred rescale gives bitwise the same numerics as r51; the wider threshold raises max_abs on the long rows as stated above and leaves the short rows unchanged. 🤖 Generated with [Claude Code](https://claude.com/claude-code)  ## Summary by CodeRabbit * **Performance** * Updated paged-attention planning for long sequences, including more selective splitting of final partial waves. * Optimized attention output reduction and row scheduling to better handle full and partial work tiles. * **Reliability** * Improved synchronization across attention tiles to ensure completion is observed consistently during processing.  --------- Co-authored-by: Yingyi Huang <averyh@nvidia.com> Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>

yyihuang requested review from Anerudhan, Aneureka, Jingfan-Sun, YangXu1990uiuc, aleozlx, bkryu, cyx-6, dhiraj113, feih-nv, jiahanc, jimmyzho, kahyunnam, nv-yunzheq, qiching, qsang-nv, saltyminty, samuellees, sricketts, yongwww and yzh119 as code owners September 27, 2026 04:32

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[CAKE] Long-term CAKE-generated Kernel Progress Tracker #4254

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yyihuang changed the title ~~perf(cake_mla_varq_dcp_decode): record the second-round attribution and add a query-pattern benchmark option~~ perf(cake_mla_varq_dcp_decode): drop the package README and add a query-pattern benchmark option (second-round attribution, no module change) Sep 27, 2026

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yyihuang merged commit 15a7e17 into flashinfer-ai:main Sep 27, 2026
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perf(cake_mla): kimi_k3 shape, regenerate both architectures for the r52 kernel (deferred O rescale, wider long-request threshold) #5602

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[CAKE] Attention Kernel Progress Tracker #6594

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[cake deslop] nvfp4_mla_decode + cake_mla_varq_dcp_decode (2): fold DCP clones left by #5868 (−14,858 lines), strip dead <sm_100 branches #6673

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Unit Tests

Multi-GPU and Multi-Node Tests — 5/6 passed

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