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feat(moe): extend cuTile fused MoE to datacenter Blackwell (SM100/SM103) - #5008

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yifeis-nv:cutile-moe-datacenter-blackwell

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📌 Description

Extend the cuTile fused MoE backend (added in #4646) to datacenter Blackwell — SM100 (B200) and SM103 (B300) — for both BF16 and NVFP4 W4A4.

The cuTile MoE kernels (flashinfer/fused_moe/cutile/moe.py, fp4.py) are architecture-agnostic cuda.tile DSL — there is no SM branching or arch intrinsic in the kernels; tileiras+NVRTC lower them per target SM. Adding datacenter Blackwell is therefore a runner/config-layer change only, no kernel work:

  • flashinfer/fused_moe/api.py: add 100, 103 to _CUTILE_BF16_ARCHS and _CUTILE_NVFP4_ARCHS.
  • flashinfer/fused_moe/runners.py: add SM100/103 entries to the two arch-keyed BF16 tables (_CUTILE_BF16_DEFAULT_GEMM_CONFIGS default-tile map, and the prefill_threshold in _candidate_non_gated_block_sizes). Seeds mirror the SM90 datacenter profile and are refined by autotuning (the full config set is still searched when autotune is on). NVFP4 has no arch-keyed table, so it needs only the tuple widen.
  • tests/moe/test_unified_moe_cutile.py: widen the human-readable skip-guard reason strings. No new parametrization is needed — the guards gate on Config.supported(cc), so the existing BF16/NVFP4 test matrix auto-activates on the new arches.

The runtime is_cuda_tile_available() gate (flashinfer/cutile/cutile_common.py) already probes tileiras/NVRTC per device, so an env whose toolchain lacks SM100/103 still fails closed.

Draft — pending on-hardware validation. Code is complete and passes static checks (py_compile, ruff check/format, scope audit). Numeric parity vs compute_reference_moe and a cuTile-vs-CUTLASS autotune sweep on real B200 (sm100) / B300 (sm103) are still to be run; the SM100/103 tile-config seeds will be confirmed/refined from that sweep, and before/after perf numbers with named GPUs will be added here per CONTRIBUTING.

🔍 Related Issues

Follow-up to #4646 (cuTile fused MoE backend).

🚀 Pull Request Checklist

✅ Pre-commit Checks

  • I have installed pre-commit by running pip install pre-commit (or used your preferred method).
  • I have installed the hooks with pre-commit install.
  • I have run the hooks manually with pre-commit run --all-files and fixed any reported issues.

🧪 Tests

  • Tests have been added or updated as needed. (Existing tests/moe/test_unified_moe_cutile.py matrix auto-covers SM100/103 via the supported-arch skip guards.)
  • All tests are passing (unittest, etc.). Pending on-hardware B200/B300 run — see Description.

Reviewer Notes

Kept the change strictly additive so it cannot affect the already-shipped SM89/90/120/121 paths. The one thing worth a close look is the NVFP4 W4A4 path on datacenter Blackwell: it has no arch-keyed config table (its heuristics are shape-driven), so correctness should carry over, but the FP4 MMA path on SM100/103 will get an explicit numeric-parity run before this leaves Draft. Perf headroom on _CUTILE_W4A4_GEMM_CONFIGS re-tuning for datacenter is noted as a follow-up.

Widen the cuTile MoE arch gates to cover SM100 (B200) and SM103 (B300)
for both BF16 and NVFP4 W4A4. The kernels are architecture-agnostic
cuda.tile DSL, so this is a runner/config-layer extension only:

- api.py: add 100/103 to _CUTILE_BF16_ARCHS and _CUTILE_NVFP4_ARCHS
- runners.py: seed SM100/103 entries in the two arch-keyed BF16 tables
  (_CUTILE_BF16_DEFAULT_GEMM_CONFIGS default-tile map, prefill_threshold);
  seeds mirror the SM90 datacenter profile and are refined by autotune
- tests: widen the skip-guard reason strings; the guards auto-activate
  the existing test matrix on the new arches via Config.supported(cc)

NVFP4 has no arch-keyed table, so it needs only the tuple widen. The
runtime is_cuda_tile_available() gate already probes tileiras/NVRTC per
device.

Co-Authored-By: Claude <noreply@anthropic.com>
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