bench: compare DeepSeek MoE against pure TRTLLM BF16 - #4985
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Included review availability: Your plan provides up to 8 included reviews per hour; 7 remain after this review. 📝 WalkthroughWalkthroughThe benchmark unifies TRTLLM NVFP4 and BF16 execution under ChangesTRTLLM precision benchmark
Estimated code review effort: 4 (Complex) | ~45 minutes Merge Risk: ⚪ Minimal · up to This benchmark-only change adds separate BF16 and NVFP4 TRTLLM comparison paths, backend selection, profiling, and reporting. No concrete merge-blocking risk remains. Sequence Diagram(s)sequenceDiagram
participant BenchmarkCLI
participant bench_trtllm
participant RoutedInputCache
participant TRTLLM
BenchmarkCLI->>bench_trtllm: select NVFP4 or BF16 precision
bench_trtllm->>RoutedInputCache: reuse routed workload inputs
bench_trtllm->>TRTLLM: dispatch logits or pre-routed execution
TRTLLM-->>bench_trtllm: return benchmark result
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In `@benchmarks/bench_moe_deepseek.py`:
- Around line 1244-1247: Update the backend-selection logic around
run_trtllm_bf16 and the other backend conditions to reject any --profile-backend
value that is not among the selected --backends, or explicitly let the profile
backend override backend selection. Ensure incompatible combinations such as
cutedsl with trtllm-bf16 fail instead of completing without a workload.
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📌 Description
@HumansAnd
Compare CuTe DSL W4A16/W4A4 MoE against pure TRTLLM BF16 using the same DeepSeek-V3 source inputs. Extend
benchmarks/bench_moe_deepseek.pywith BF16 and NVFP4 precision modes in the existingbench_trtllmhelper.TrtllmBf16Config.prepare_weightsapplies gated row reorder and BlockMajorK layout outside timing, with no quantization.TRTLLM NVFP4/TRTLLM BF16output andtrtllm-nvfp4/trtllm-bf16selectors for benchmarking/profiling; shared routing, autotuning and measurement setup with explicit precision branches. Both precisions reuse the same cached routed realization per input row.--no-fused-finalizeapplies to CuTe. TRTLLM retains native finalize; FP4 activation flags do not affect pure BF16.Source and environment
1ac2233d43df747af455ed4a8406d7439d686d9f(FlashInfer 0.6.18), used for all nine sweeps. Implementation head:2079fa00c4a2a0fb2e95bb284978a703653a4830. The nine sweeps precede the shared-helper/name/CLI-validation updates. Separate diagnostic measurements below identify their own source commits; they do not replace the original sweeps. Paired refactor correctness validation is linked in Tests.CUDA_VISIBLE_DEVICES=0, SM103, 148 SMs, 267.7 GiB) on an eight-B300 host; driver 590.48.01 and image CUDA compatibility library 595.58.03.nvcr.io/nvidia/pytorch:26.05-py3; digestnvcr.io/nvidia/pytorch@sha256:222d8b18e671be5c3ef91cb41727a2572a0b23f59ded6c39f373a96946f6f2ba.nvcc V13.2.78), PyTorch2.12.0a0+5aff3928d8.nv26.05, Python 3.12.3, CuTe DSL[cu13]==4.7.0,cupti-python==13.2.0,nvidia-cuda-cupti==13.2.86,apache-tvm-ffi==0.1.13.post3;nvidia-cuda-nvdisasm==13.3.73is the DSL disassembler dependency, while compiler/runtime remain CUDA 13.2.e713467f; the measured Git checkout is1ac2233d. Their difference only shares routed benchmark inputs across TRTLLM precisions. Warm compilation caches are retained.Reproduction and configuration
Run inside the image above. Setup the exact measured source; the optional EP-transport build is disabled because no communication is performed.
Run each command below from that checkout. All commands use logits routing, wrapper API, TP1, initial activation quantization included, CUDA graphs, CUPTI and autotuning. The existing order was per-token 1, RL 1, per-token 2, RL 2, per-token 3, RL 3. Only the added per-tensor variant was subsequently run three times consecutively. Every repetition starts a fresh Python process.
Inference per-tensor —
Per-token activation: False: omit--use-per-token-activation; use the existing global-scale path, 4over6 disabled, FP4 quantization fast math enabled, CuTe fused atomic finalize. The default CLI includes CUTLASS NVFP4 in this configuration.env \ -u FLASHINFER_NVFP4_4OVER6 \ -u FLASHINFER_NVFP4_4OVER6_E4M3_USE_256 \ -u FLASHINFER_NVFP4_4OVER6_ERR_MODE \ -u FLASHINFER_NVFP4_4OVER6_ERR_USE_FAST_MATH \ -u FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH \ CUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 MAX_JOBS=8 \ python3 benchmarks/bench_moe_deepseek.py \ --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096 \ --ep 8 --warmup 10 --iters 100 --routing-input-mode logits \ --include-activation-quantInference per-token —
Per-token activation: True: per-token activation scaling, 4over6 disabled, FP4 quantization fast math enabled, CuTe fused atomic finalize. CUTLASS is omitted because it does not consume per-token scales.env \ -u FLASHINFER_NVFP4_4OVER6 \ -u FLASHINFER_NVFP4_4OVER6_E4M3_USE_256 \ -u FLASHINFER_NVFP4_4OVER6_ERR_MODE \ -u FLASHINFER_NVFP4_4OVER6_ERR_USE_FAST_MATH \ -u FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH \ CUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 MAX_JOBS=8 \ python3 benchmarks/bench_moe_deepseek.py \ --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096 \ --ep 8 --warmup 10 --iters 100 --routing-input-mode logits \ --include-activation-quant --use-per-token-activationDeterministic RL —
Per-token activation: True: per-token 4over6 MSE, E4M3 max 256, error fast math enabled, FP4 quantization fast math disabled, CuTe two-stage finalize. This is the requested configuration name, not a full-model determinism claim; CUTLASS is omitted.env \ -u FLASHINFER_NVFP4_4OVER6 \ -u FLASHINFER_NVFP4_4OVER6_E4M3_USE_256 \ -u FLASHINFER_NVFP4_4OVER6_ERR_MODE \ -u FLASHINFER_NVFP4_4OVER6_ERR_USE_FAST_MATH \ -u FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH \ CUDA_VISIBLE_DEVICES=0 FLASHINFER_DISABLE_VERSION_CHECK=1 MAX_JOBS=8 \ FLASHINFER_NVFP4_4OVER6=1 \ FLASHINFER_NVFP4_4OVER6_E4M3_USE_256=1 \ FLASHINFER_NVFP4_4OVER6_ERR_MODE=MSE \ FLASHINFER_NVFP4_4OVER6_ERR_USE_FAST_MATH=1 \ FLASHINFER_DISABLE_FP4_QUANT_FAST_MATH=1 \ python3 benchmarks/bench_moe_deepseek.py \ --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096 \ --ep 8 --warmup 10 --iters 100 --routing-input-mode logits \ --include-activation-quant --use-per-token-activation --no-fused-finalizeBenchResultrecords after measurement; original CLI/timing functions are unchanged. All nine processes exited 0. All 507 captured latencies (6×13×4 + 3×13×5) were checked against the printed values before aggregation.Complete raw performance results
All nine complete result tables follow. Backend names and table spacing are normalized for display; decorative divider lines are omitted. Original logs and captures remain unchanged, as do every result value and column. Identical printed configuration headers are shown once per three-run group. Raw latency prints to 0.001 ms; raw speedups use unrounded values. The existing six per-token/RL measurements remain unchanged; only the three per-tensor runs were added.
Inference per-tensor — printed configuration for all three runs:
Inference per-tensor run 1 — 13 token counts, 5 backends
Inference per-tensor run 2 — 13 token counts, 5 backends
Inference per-tensor run 3 — 13 token counts, 5 backends
Inference per-token — printed configuration for all three runs:
Inference per-token run 1 — 13 token counts, 4 backends
Inference per-token run 2 — 13 token counts, 4 backends
Inference per-token run 3 — 13 token counts, 4 backends
Deterministic RL — printed configuration for all three runs:
Deterministic RL run 1 — 13 token counts, 4 backends
Deterministic RL run 2 — 13 token counts, 4 backends
Deterministic RL run 3 — 13 token counts, 4 backends
Derived performance summary
Latencies are medians of three fresh-process runs, calculated from unrounded captures and displayed in milliseconds to three decimal places. Each W4A16 speedup is the named TRTLLM baseline's median latency divided by the CuTe DSL W4A16 median latency at that token count. These are ratios of medians; values above 1 mean W4A16 is faster; values below 1 mean W4A16 is slower. Both NVFP4 and pure BF16 comparisons are explicit.
Inference per-tensor — median of three runs
Inference per-token — median of three runs
Deterministic RL — median of three runs
BF16 performance investigation
Finding: the W4A16 advantage is present in GPU expert computation. TRTLLM BF16 tuning is active; exhaustive native-tactic checks on the actual inputs do not close the gap. Preparation, tuning, L2 flushing and host dispatch are outside the reported CUPTI GPU span. Independent single-call graph events reproduce the ordering. These diagnostics supplement the unchanged nine sweeps.
Provenance: profiles, actual-input tactic sweep and event controls use
2079fa00c4a2a0fb2e95bb284978a703653a4830on the same retained B300/CUDA 13.2 image above. Nsight Systems 2026.2.1, GPU 0; tactic diagnostics GPU 1, serialized with GPU 0 work. Initial cache/default audit usesa3fce87d5beec29775e9bc3917df99ba6bc4db9c. Naming commitd0caa842and profiling-only commit2079fa00are separate; normal benchmark functions/timing remain unchanged from the refactor validation source.Autotuning: 2,852 successful native candidate profiles across 21 token buckets, zero failures; all ten measured warmup/capture dispatches used nonfallback cache hits with tuning disabled. The selected tactic reaches the native launcher. At 32 tokens, all 352 actual-input candidates give a best 284.5635 µs versus 287.3155 µs for the selected baseline (about 1%, single sweep). At 4096, the selected
(128,0)is also the exhaustive eight-candidate winner at 529.3520 µs. Default-1is ~15% slower there. The v1 tuner's synthetic routing activates 11/30 local experts at 32/4096, versus 21/32 on actual inputs; shorter synthetic probe times therefore are not the final benchmark latency. The exhaustive actual-input sweep checks this selection concern directly.TRTLLM BF16 tuned/default controls (µs; each cell is a 100-iteration median; 3 alternating pairs):
All actual-input native candidates (median of 100 iterations, µs; one sample each). Each CSV row lists latencies in ascending contiguous config-ID order;
(tileN, config)is the native tactic. This includes every 352/8 enumerated candidate plus default.Nsight Systems complete device breakdown (µs): 20 cold-L2, one-call graph replays per case after tuning and three uncaptured replays. Every non-dash activity cell is the mean of 20 instances; both temporary-zero kernels are shown separately. All target kernels/memsets are accounted for inside synchronized
moeNVTX ranges; each contains onecudaGraphLaunch. The 20 separately labeled L2 flushes are excluded. Kernel sums are diagnostic, not latency: programmatic dependent launch allows dependent kernel intervals to overlap. GPU span measures the first activity start through last activity end; uncovered gaps use the union of intervals. Inference profiles cover both inference activation variants because those flags do not change W4A16 or TRTLLM BF16; RL is separately profiled.Inference:
Deterministic RL:
Kernel mapping: top-k=
deepseek_v3_topk_kernel/routingMainKernel; route map=routingIndicesClusterKernel/routingIndicesCoopKernel; temporary zeros=vectorized_elementwise_kernel; permute/unpermute=moePermuteKernel/moeUnpermuteKernel; CuTe GEMMs=Sm100W4A16GroupedGemmKernelin launch order; TRTLLM BF16 GEMMs=bmm_Bfloat16_Bfloat16Bfloat16...(FC1 hasswiGlu); native finalize=finalizeKernel/finalizeKernelVecLoad. CuTe inference GEMM2 includes atomic finalize; RL uses the separate unpermute row. At 32 tokens both GEMMs explain the gap; at 4096 the largest difference is GEMM1, with native finalize also contributing. TRTLLM BF16 has no uncovered device gaps in these traces.Independent timer control: same tuned callable, one call per graph, 100 samples after 10 warmups; zero a 2×L2 byte buffer and synchronize before each start event, then
start.record(); graph.replay(); end.record(); end.synchronize(). CUPTI separately measures the same prepared callable. Every case passed with finite outputs. Table contains every case's median in µs. Event intervals add roughly 4–6 µs but retain the gap; host submission cannot explain the BF16 slowdown. Warm-cache results are sequential diagnostics, not an isolated cache speedup claim. Ordinary--no-cuptiis not this control: it uses ten-call graphs and rotates only input kwargs, leaving closure-held weights unrotated.Nsight Compute: fixed normal-tuned tactics
2079fa00. Tactics were recorded during normal tuning before NCU injection, then fixed by a diagnostic helper; all captured calls had tuning disabled. Each report contains exactly FC1 (with SwiGLU) and FC2, nine replay passes each. Node replay flushes caches and isolates PDL kernels: these durations are diagnostics, not additive end-to-end latency.(8, 37)at 32;(128, 1)at 4096. CuteDSL W4A16 uses the same tactic for both GEMMs:((128, 8, 256), (2, 1), True)at 32;((256, 128, 256), (2, 1), True)at 4096.Raw counters below: R/W = DRAM bytes; D/T/S = DRAM throughput / tensor-pipe activity / SM throughput (% of sustained elapsed peak); LD/ST = local-memory sectors; warps = active warps per active SM cycle; A/T = achieved/theoretical occupancy (%).
Remaining launch counters (all eight kernels): occupancy limits = 32 blocks, 1 block by registers, 1 by shared memory; warp limit = 5/8 blocks for BF16 FC1/FC2 and 4 for W4A16. Cluster dimensions =
(2,1,1), except BF16 at 32 uses(1,1,1).occupancy_cluster_pct= 3.12%;occupancy_cluster_gpu_pct= 0.59/0.39% for BF16 FC1/FC2 and 0.78% for both W4A16 kernels (launch estimates, not measured GPU activity). Full raw CSV/report metadata is retained.Interpretation: at 4096, BF16 still reaches 84–86% DRAM throughput with 41–44% tensor activity; W4A16 FC1 reaches 87% tensor activity. BF16 reads 3.025 GB versus W4A16's 0.960 GB. EP8 leaves 3715 local assignments across 32 experts (116/expert); 4096 is not each expert's GEMM M. No local load/store traffic was measured in any kernel. Registers and shared memory both limit residency to one block/SM; low occupancy alone does not establish an avoidable defect. These counters support a bandwidth explanation and do not demonstrate a spilling or launch-overhead bug.
Public CLI equivalent on
2079fa00: TRTLLM BF16 at 32 passed normal cache save then fresh-process--no-autotuneload (both exit 0, target cache hit, no retuning, unchanged cache hash). The measured counters above used the helper-frozen tactics, not this smoke cache. Run in the same inference environment with NVFP4 overrides unset. Require a target-operationConfig cache hit; missing/incompatible caches can otherwise fall back.Why 4096 remains bandwidth-sensitive: the actual EP8 routing has 3715/32 = 116.09 rows per expert. Useful BF16 GEMM FLOPs divided by unique weight bytes give 116.09 FLOP/byte; including minimum activation traffic gives about 108–112. The advertised dense BF16 rate is 36 PFLOPS/node ÷ 2 ÷ 8 = 2.25 PFLOPS/GPU (NVIDIA HGX specifications); with 8 TB/s HBM, the ideal crossover is about 281 FLOP/byte. These are analytical peak bounds, supported here by the measured DRAM counters. Tile128 pads to 40 tiles/5120 slots (72.56% useful rows). The 3.025 GB measured BF16 reads are close to 2.819 GB unique weights and below 3.523 GB if every token tile reread them. Compression moves W4A16 GEMM1 toward compute saturation; equal tensor-core input precision does not give equal memory traffic.
Reproduce the eight Nsight traces from the implementation checkout and image above. Output files remain on the retained devbox; no compilation caches are removed.
Aggregate all GPU activities contained by each synchronized
moeNVTX range, including target memsets; verify 20 ranges and one graph launch per range. Report per-kernelsum(end-start)/20, per-range GPUmax(end)-min(start), and CPU graph-launch duration separately. Excludel2_flush; do not sum kernel durations as wall-clock latency. These are single-GPU local-expert diagnostics, not distributed or full-model speedups.Interpretation and limits
🔍 Related Issues
Related implementation and benchmark configurations: #4048.
🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.
✅ Pre-commit Checks
pre-commitby runningpip install pre-commit(or used your preferred method).pre-commit install.pre-commit run --all-filesand fixed any reported issues.🧪 Tests
Tests have been added or updated as needed.
All tests are passing (
unittest, etc.).Original measured source: seven existing BF16 GPU tests passed (310 deselected); eight independent reference cases passed with unchanged
rtol=atol=0.03, three exact eager repeats and three exact CUDA-graph replays per case. BF16 CLI/profiler smoke passed. Complete original test output, helper and commands.Shared-helper refactor
a3fce87d: 43 paired GPU cases matched measured source1ac2233dfor public entry points, bound kernel arguments, finalized output bytes and timing inputs; renamed selectors and NVFP4 profiler smoke passed; an excluded profiling backend is rejected with exit 2. Autotuning was disabled for these bounded equivalence checks. Complete refactor validation and reproduction.Later head
2079fa00: printed-name fixtures and external-profiler NVTX ranges are validated separately; the five benchmark functions and non-profile timing branch remain AST-identical to the 43-case refactor source. Those 43 cases are attributed to the refactor commit above.Static scope: file-scoped pre-commit hooks, Ruff, formatting, Python compilation and
git diff --checkpassed. Mypy is skipped by the configured hook because this benchmark is outside itsflashinfer/scope. No upstream test files were changed; all-files hooks and the full repository test suite were not run. These correctness checks do not replace the nine performance sweeps.🔬 Experimental Track
flashinfer/experimental/and/or an@flashinfer_experimental_api. Tracking issue: #tests/experimental/and were validated on the intended hardware; a runnable example is included.flashinfer/aot.py, and no experimental backend is reachable frombackend="auto"withoutFLASHINFER_ALLOW_EXPERIMENTAL_AUTO_BACKENDS=1. (Calling an@flashinfer_experimental_apior naming a backend explicitly is itself the opt-in and needs no environment variable.)Reviewer Notes
Please review the precision-specific TRTLLM weight/scale arguments, shared routing and timing boundary, explicit backend/finalize labels, and the three configuration definitions. All nine raw tables and both W4A16 baseline speedup columns are above; complete validation output is linked in Tests. Unchecked all-files/full-suite items reflect the stated scope.
Summary by CodeRabbit
New Features
trtllm-bf16backend to benchmark selection, validation, tables, speedup reporting, and command-line help.Bug Fixes