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First W4A16 adopter of the shared disk cache (flashinfer-ai#4331), following the direct-micro adopter pattern (flashinfer-ai#4701): TVM-FFI env-stream compile, raw pointer + DLTensor-anchor launch ABI, and a dedicated b12x_moe_w4a16 module directory with W4A16-wide source-file invalidation. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
…ache Second W4A16 adopter: the entry's fc1/activated params are already DLTensors and double as the env-stream anchors, so only the compile path changes (fake env stream, --enable-tvm-ffi, dedicated module artifact with a full-cache-key digest in the name). No launch-site change: the standalone activation entry has no in-repo launcher. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
…ache The production-launched heavyweight of the W4A16 family. Compile keeps its OptLevel(3) as an option string alongside --enable-tvm-ffi and a fake env stream; launch converts to the TVM-FFI ABI (raw data_ptr ints for the two pointer params, no stream argument, a current-stream guard). Extent policy, established empirically against the test battery: TVM-FFI exact-checks every DLTensor's baked extent at call time, yet extents never bound a device-side access (the kernels index through stride math bounded by their scalar arguments), and the kernel cache key does not track the m bucket -- one artifact serves all m for a given specialization. So only m-independent tensors with real size contracts (weights, scales, global scales, activation_amax) bake true extents and pass full flat views, while every m-, route- or scratch-capacity tensor bakes (1,) barrier-style (flashinfer-ai#4701) and passes a length-1 view: an extent that varies with an unkeyed fact would poison cross-m reuse of the cached artifact (the historical bakes -- routed rows, the c_tmp max floors, the 4*256+2 locks -- were exactly such fictions, latent only because nothing checked them before TVM-FFI). The const-expr-dead activation_amax gets an F32-scratch stand-in cut to its baked 2E extent when collection is off. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
Final W4A16 adopter, under the extent policy established on the fused entry: weights, scales and global scales bake true extents; the m-, route- and scratch-capacity tensors (a, c, topk, packed routes, block experts, c_tmp, locks) bake (1,). The standalone gemm entry has no in-repo launcher, so its verification is the compile/persist/reload round-trip; the family's device codegen is exercised by the fused battery. With all four entries converted, the in-process-only cached_compile/KernelCompileSpec imports are dropped. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
Factors the on-disk kernel-name construction into a single pure helper (readable facts + a sha256 digest of the entry's full cache_key) and pins the contract it relies on: digest sensitivity across every value kind the keys carry (incl. float-sign and None-vs-0 collisions that sanitized text alone would miss), determinism, prefix separation, and symbol safety -- plus GPU tests for the disk round-trip surviving an in-process cache clear and CUDA-graph capture on a warm-loaded artifact. Mirrors the naming-contract suite the direct-micro adopter added in test_b12x_moe_kernel_cache.py, adapted to the digest-based naming scheme. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
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Included review availability: Your plan provides up to 8 included reviews per hour; 5 remain after this review. 📝 WalkthroughWalkthroughThe SM12x W4A16 CuTe-DSL compilation paths now use shared hashed disk artifacts with source invalidation tracking. Launches use TVM-FFI-compatible pointer and tensor arguments, current-stream checks, buffer validation, and updated top-k-sum output anchoring. ChangesW4A16 disk-cache adoption
Estimated code review effort: 4 (Complex) | ~60 minutes Merge Risk: ⚪ Minimal · up to This change persists and reuses W4A16 MoE kernel artifacts across processes while retaining shared activation artifacts across row counts. The corrected extent policy and isolated warm-load coverage leave no concrete current-head merge risk. Sequence Diagram(s)sequenceDiagram
participant W4A16Launcher
participant build_and_load_cute_dsl_kernel
participant DiskArtifact
participant W4A16CUDAKernel
W4A16Launcher->>build_and_load_cute_dsl_kernel: request W4A16 specialization
build_and_load_cute_dsl_kernel->>DiskArtifact: load or create hashed artifact
build_and_load_cute_dsl_kernel->>W4A16CUDAKernel: return compiled kernel
W4A16Launcher->>W4A16CUDAKernel: pass TVM-FFI pointers and tensor views
W4A16CUDAKernel-->>W4A16Launcher: write kernel outputs
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Description checkExplanation The description explains the purpose, scope, linked issue, design decisions, performance impact, verification results, and updated tests. It does not reproduce the repository checklist sections, but the missing checklist details are non-critical because the required changes and validation are documented. Full details: Linked Issues checkExplanation The PR satisfies issue Full details: Out of Scope Changes checkExplanation The changes remain within issue
✨ Finishing Touches 💡 1🛠️ Fix failing CI checks 💡
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Inline comments:
In `@flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.py`:
- Line 5946: Update W4A16ActivationKernel.__cache_key__ to include
_m_specialization_key(rows), ensuring distinct in-process and disk artifacts for
each activation row bucket. Add a regression test that clears the cache,
compiles both row buckets, and verifies their artifact names differ.
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Review follow-up (CodeRabbit): the activation entry was converted before the extent policy that the fused/gemm commits established, and its fake extents still varied with the row bucket while the cache key -- by design, matching the in-process replace(cached, rows=rows) reuse -- does not. Rather than keying the bucket (which would split artifacts and contradict the existing cross-row reuse semantics), the m-varying extents now bake (1,) like every other unkeyed-capacity tensor, so one artifact genuinely serves all rows. Adds a regression test pinning the sharing: both row buckets resolve to a single artifact, warm-launchable at either row count. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
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@coderabbitai The activation finding is correct -- that entry was converted before the extent policy the later fused/gemm commits established, and was never brought under it. Fixed in 878c8d0, though by the policy-consistent resolution rather than keying the bucket: the row bucket is deliberately absent from the cache key (the in-process cache reuses one compiled kernel across rows via |
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Inline comments:
In `@tests/moe/test_b12x_w4a16_kernel_cache.py`:
- Around line 213-214: The artifact assertion should not depend on unrelated
persistent files in matching module directories. Update the test around
_w4a16_module_artifacts() and clear_w4a16_kernel_cache() to isolate compilation
in a test-local JIT directory, or assert the specific expected artifact name
rather than requiring exactly one activation artifact.
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Tip For best results, initiate chat on the files or code changes. 🧩 Analysis chain🏁 Script executed: #!/bin/bash
set -euo pipefail
git show --stat --oneline 878c8d0a
git show --format=fuller --find-renames --find-copies 878c8d0a -- \
flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.py \
tests/moe/test_b12x_w4a16_kernel_cache.py
ast-grep outline flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.py \
--items all --match 'W4A16|activation|Activation' --view expanded || true
ast-grep outline tests/moe/test_b12x_w4a16_kernel_cache.py \
--items all --match 'activation|Activation' --view expanded || true
rg -n -C 5 -e 'replace\(cached,\s*rows=rows\)' -e 'rows' -e 'extent' -e 'cache_key' -e 'artifact' \
flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.py \
tests/moe/test_b12x_w4a16_kernel_cache.pyLength of output: 151474 🏁 Script executed: #!/bin/bash
set -euo pipefail
sed -n '4818,4840p' flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.py
sed -n '5888,5955p' flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_w4a16_kernel.pyLength of output: 3481
Commit The regression test verifies one disk artifact for rows 1 and 64. It also verifies warm launches at both row counts. One documentation detail remains: Lines 5940-5943 state that ✏️ Learnings added
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Two review cleanups, no kernel-design change: the activation naming comment no longer claims the cache key carries the row bucket (it is deliberately excluded so one artifact serves all rows), and the bucket-sharing test now compiles into a test-local JIT directory (monkeypatched jit_env.FLASHINFER_JIT_DIR redirects real artifact writes, not just the scan), so artifacts accumulated in the persistent cache can no longer fail its exactly-one-artifact assertion. Signed-off-by: gavinkvx <301998139+gavinkvx@users.noreply.github.com>
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Hi team! Hope this helps! @Aneureka @bkryu Since the PR CI matrix has no SM120 runner, here is a quick summary of how this was verified locally (RTX 5090, sm_120), to make authorization/review easier:
Happy to run any additional command or config locally and paste full output same-day. When convenient, could one of you authorize CI ( @bkryu tagging you for continuity from #4317/#4701 -- this is the W4A16 rollout of that same mechanism. Please let me know, thank you! |
2 participants
Closes #4892
Summary
Routes the SM12x W4A16 CuTe-DSL MoE kernels -- the last member of the b12x kernel family compiled in-process only -- through the shared on-disk kernel cache (#4331), following the adopter pattern of the direct-micro conversion (#4701). All four compile entries in
moe_w4a16_kernel.pyare converted (topk_sum, activation, fused_moe, gemm); the production-launched fused entry additionally converts its launch site to the TVM-FFI ABI.Measured on RTX 5090 (sm_120): the W4A16 test batteries drop from 4.73 s → 0.61 s (route-pack) and 8.27 s → 3.71 s (unified, w4a16 selection) on warm processes; per-specialization cold compiles of 0.6–2.0 s (≈7.3 s across a serving-like two-config sweep) are paid once per machine instead of once per process. This is a seconds-scale per-process tax, not the minute-scale direct-micro compiles; it scales with model configs × batch buckets × ranks × restarts and is re-paid by every test process during development.
Extent policy (the substantive design point)
TVM-FFI exact-checks every DLTensor's baked extent at call time, yet extents never bound a device-side access: the kernels index through stride math bounded by their scalar arguments, and the pre-FFI launch passed buffers whose sizes bore no relation to the fake shapes. The kernel cache keys also do not track the m bucket, so one artifact serves all m for a given specialization. The policy that follows, applied to all four entries:
(1,)barrier-style (perf(moe): persist the b12x direct-micro CuTe-DSL kernel to the disk cache #4701) and passes a length-1 view -- an extent that varies with an unkeyed fact would poison cross-m reuse of the cached artifact.This surfaced three pre-existing fictions in the historical fake shapes, latent only because nothing checked them before TVM-FFI: the FC2 fake ignored TC-decode mode (which writes the m×hidden output buffer, not routed rows), the c_tmp fakes carried a
max(..., 4*256*mbs*256)floor unrelated to the realpacked_gemm_scratch_elementsallocation, and the locks fake assumed a ≤256-SM part while the real workspace followssms*4+2.Other notes for review
OptLevel(3)becomes--opt-level 3 --enable-tvm-ffi; entries that used the default compile at--opt-level 2 --enable-tvm-ffi, matching the direct-micro default.pack_topk_routes_by_expertalready enforces the same contract in this file.activation_amaxparam gets an F32-scratch stand-in cut to its baked 2E extent.cache_key; injectivity over the codegen parameters is inherited from the key that already gates the in-process caches.tests/moe/test_b12x_w4a16_kernel_cache.pypins that contract (digest sensitivity incl. float-sign/None-vs-0, determinism, symbol safety) plus GPU disk round-trip and CUDA-graph capture on a warm-loaded artifact.b12x_moe_w4a16module directory avoids the mutual-invalidation hazard of sharing a per-module source hash with the MMA or direct-micro adopters. Independent of perf(moe): persist the b12x direct-micro CuTe-DSL kernel to the disk cache #4701: the cache primitive is on main, and this rebases trivially over that PR when it lands.Verification (RTX 5090, sm_120)
Full W4A16 battery green on cold and warm processes:
tests/moe/test_b12x_w4a16_route_pack.py(64),tests/moe/test_unified_moe_b12x.py -k w4a16(23, incl. CUDA-graph capture/replay and dispatch-accuracy conformance), and the new cache-contract suite (6).Summary by CodeRabbit
New Features
Bug Fixes
Tests