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fix(moe): pad BF16 TRTLLM-Gen intermediates to 128 KiB #4319

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Merged
leejnau merged 5 commits into from
Aug 10, 2026
Merged

fix(moe): pad BF16 TRTLLM-Gen intermediates to 128 KiB #4319

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bbfaff4
fix(moe): pad BF16 TRTLLM-Gen intermediates to 128 KiB
nvpohanh Aug 3, 2026
1812142
Merge branch 'main' into fix/bf16-moe-tma-128k
nvpohanh Aug 4, 2026
c8a3734
Merge branch 'main' into fix/bf16-moe-tma-128k
nvpohanh Aug 5, 2026
d428307
Merge branch 'main' into fix/bf16-moe-tma-128k
nvpohanh Aug 6, 2026
ce984d8
Merge branch 'main' into fix/bf16-moe-tma-128k
nvpohanh Aug 10, 2026
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13 changes: 11 additions & 2 deletions csrc/trtllm_fused_moe_kernel_launcher.cu
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Original file line number Diff line number Diff line change
Expand Up @@ -896,10 +896,19 @@ class Bf16MoeLauncher : public FusedMoeLauncher {
void prepare_moe(int64_t& moe_tactic) override {
FusedMoeLauncher::prepare_moe_common(moe_tactic);

// Blackwell TMA may select BASE_128KB address generation from the logical tensor-map shape.
// Keep at least 128 KiB mapped from each activation base, as the quantized launchers do below.
int32_t max_num_padded_tokens = workspace.total_max_padded_tokens;
gemm1_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,
int32_t max_num_padded_tokens_gemm1 =
tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(
max_num_padded_tokens, args->intermediate_size,
btg::dtypeGetNumBits(btg::Dtype::Bfloat16));
int32_t max_num_padded_tokens_gemm2 =
tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(
max_num_padded_tokens, args->hidden_size, btg::dtypeGetNumBits(btg::Dtype::Bfloat16));
gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size}, dl_bfloat16,
hidden_states.device());
gemm2_output = alloc_tensor({max_num_padded_tokens, args->hidden_size}, dl_bfloat16,
gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,
hidden_states.device());

workspace.hidden_states_scale_linear = nullptr;
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