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feat: add sm100 cp delta rule prefill - #4078

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jiahanc merged 20 commits into
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cp_delta_rule_sm100
Aug 5, 2026
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jiahanc merged 20 commits into
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cp_delta_rule_sm100

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@guangyunh-nv

@guangyunh-nv guangyunh-nv commented Jul 21, 2026

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📌 Description

This PR adds cp impl for delta rule.

🔍 Related Issues

🚀 Pull Request Checklist

✅ Pre-commit Checks

  • I have installed pre-commit by running pip install pre-commit (or used your preferred method).
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🧪 Tests

  • Tests have been added or updated as needed.
  • All tests are passing (unittest, etc.).

Reviewer Notes

GPU: NVIDIA B300 SXM6 AC [Blackwell (SM100)]
Models: Qwen3.5 family (397B, 122B, 35B, 27B, 9B, 4B, 2B, 0.8B), d=128

Heads            Seqlens           h_qk  h_v    FI Blackwell (SM100)   TFLOPS  FLA/Triton   Speedup
---------------------------------------------------------------------------------------------------
397B/122B TP8    1x65536              2    8                  0.343ms   100.2      2.065ms     6.02x +
397B/122B TP8    1x32768              2    8                  0.213ms    80.7      1.048ms     4.92x +
397B/122B TP8    1x16384              2    8                  0.148ms    58.2      0.531ms     3.60x +
397B/122B TP8    1x8192               2    8                  0.114ms    37.5      0.269ms     2.35x +
397B/122B TP8    1x4096               2    8                  0.084ms    25.5      0.147ms     1.74x +
397B/122B TP8    1x2048               2    8                  0.070ms    15.4      0.087ms     1.25x +
397B/122B TP8    6144+2048            2    8                  0.110ms    39.0      0.223ms     2.03x +
397B/122B TP8    4096+4096            2    8                  0.102ms    42.0      0.176ms     1.73x +
397B/122B TP8    2048+6144            2    8                  0.109ms    39.6      0.223ms     2.06x +
397B/122B TP8    1024+7168            2    8                  0.114ms    37.8      0.247ms     2.17x +
397B/122B TP8    2048x4               2    8                  0.113ms    38.1      0.130ms     1.15x +
397B/122B TP8    1024x8               2    8                  0.046ms    92.9      0.117ms     2.53x +
397B/122B TP8    8192x8               2    8                  0.241ms   142.7      0.781ms     3.25x +
397B/122B TP8    8192x16              2    8                  0.244ms   281.1      1.546ms     6.32x +
397B/122B TP8    8192x32              2    8                  0.499ms   275.5      3.055ms     6.12x +

397B/122B TP4    1x65536              4   16                  0.569ms   120.7      2.595ms     4.56x +
397B/122B TP4    1x32768              4   16                  0.326ms   105.3      1.303ms     3.99x +
397B/122B TP4    1x16384              4   16                  0.195ms    87.9      0.670ms     3.43x +
397B/122B TP4    1x8192               4   16                  0.130ms    66.2      0.342ms     2.63x +
397B/122B TP4    1x4096               4   16                  0.097ms    44.2      0.178ms     1.83x +
397B/122B TP4    1x2048               4   16                  0.077ms    27.8      0.101ms     1.31x +
397B/122B TP4    6144+2048            4   16                  0.132ms    65.0      0.295ms     2.23x +
397B/122B TP4    4096+4096            4   16                  0.129ms    66.7      0.247ms     1.92x +
397B/122B TP4    2048+6144            4   16                  0.133ms    64.5      0.294ms     2.21x +
397B/122B TP4    1024+7168            4   16                  0.134ms    64.1      0.319ms     2.38x +
397B/122B TP4    2048x4               4   16                  0.074ms   115.5      0.213ms     2.87x +
397B/122B TP4    1024x8               4   16                  0.049ms   174.3      0.218ms     4.42x +
397B/122B TP4    8192x8               4   16                  0.243ms   282.4      1.555ms     6.39x +
397B/122B TP4    8192x16              4   16                  0.495ms   277.6      3.089ms     6.24x +
397B/122B TP4    8192x32              4   16                  1.024ms   268.5      5.928ms     5.79x +

397B/122B TP2    1x65536              8   32                  1.124ms   122.2      3.663ms     3.26x +
397B/122B TP2    1x32768              8   32                  0.585ms   117.5      1.827ms     3.13x +
397B/122B TP2    1x16384              8   32                  0.321ms   107.0      0.927ms     2.89x +
397B/122B TP2    1x8192               8   32                  0.189ms    91.0      0.481ms     2.55x +
397B/122B TP2    1x4096               8   32                  0.123ms    70.1      0.249ms     2.03x +
397B/122B TP2    1x2048               8   32                  0.089ms    48.5      0.132ms     1.49x +
397B/122B TP2    6144+2048            8   32                  0.186ms    92.6      0.448ms     2.42x +
397B/122B TP2    4096+4096            8   32                  0.130ms   131.7      0.415ms     3.18x +
397B/122B TP2    2048+6144            8   32                  0.186ms    92.3      0.472ms     2.54x +
397B/122B TP2    1024+7168            8   32                  0.214ms    80.4      0.500ms     2.34x +
397B/122B TP2    2048x4               8   32                  0.078ms   221.1      0.420ms     5.40x +
397B/122B TP2    1024x8               8   32                  0.093ms   184.0      0.426ms     4.56x +
397B/122B TP2    8192x8               8   32                  0.509ms   269.8      3.125ms     6.13x +
397B/122B TP2    8192x16              8   32                  1.032ms   266.5      6.020ms     5.84x +
397B/122B TP2    8192x32              8   32                  1.962ms   280.3     12.018ms     6.13x +

397B/122B TP1    1x65536             16   64                  1.796ms   153.0      6.251ms     3.48x +
397B/122B TP1    1x32768             16   64                  0.908ms   151.4      3.096ms     3.41x +
397B/122B TP1    1x16384             16   64                  0.464ms   148.2      1.564ms     3.37x +
397B/122B TP1    1x8192              16   64                  0.242ms   142.0      0.797ms     3.29x +
397B/122B TP1    1x4096              16   64                  0.131ms   131.0      0.417ms     3.18x +
397B/122B TP1    1x2048              16   64                  0.075ms   114.9      0.218ms     2.92x +
397B/122B TP1    6144+2048           16   64                  0.188ms   182.5      0.799ms     4.24x +
397B/122B TP1    4096+4096           16   64                  0.134ms   256.8      0.801ms     5.98x +
397B/122B TP1    2048+6144           16   64                  0.189ms   182.0      0.803ms     4.25x +
397B/122B TP1    1024+7168           16   64                  0.216ms   159.2      0.804ms     3.73x +
397B/122B TP1    2048x4              16   64                  0.150ms   229.4      0.805ms     5.38x +
397B/122B TP1    1024x8              16   64                  0.184ms   187.2      0.792ms     4.32x +
397B/122B TP1    8192x8              16   64                  1.027ms   267.6      5.998ms     5.84x +
397B/122B TP1    8192x16             16   64                  1.958ms   280.8     12.012ms     6.13x +
397B/122B TP1    8192x32             16   64                  4.042ms   272.0     24.021ms     5.94x +

35B/9B/4B TP1    1x65536             16   32                  1.143ms   120.3      3.667ms     3.21x +
35B/9B/4B TP1    1x32768             16   32                  0.590ms   116.6      1.827ms     3.10x +
35B/9B/4B TP1    1x16384             16   32                  0.323ms   106.3      0.927ms     2.87x +
35B/9B/4B TP1    1x8192              16   32                  0.190ms    90.3      0.481ms     2.53x +
35B/9B/4B TP1    1x4096              16   32                  0.124ms    69.0      0.249ms     2.00x +
35B/9B/4B TP1    1x2048              16   32                  0.090ms    47.8      0.132ms     1.47x +
35B/9B/4B TP1    6144+2048           16   32                  0.186ms    92.2      0.448ms     2.40x +
35B/9B/4B TP1    4096+4096           16   32                  0.131ms   130.9      0.416ms     3.16x +
35B/9B/4B TP1    2048+6144           16   32                  0.187ms    91.9      0.473ms     2.53x +
35B/9B/4B TP1    1024+7168           16   32                  0.215ms    80.1      0.502ms     2.34x +
35B/9B/4B TP1    2048x4              16   32                  0.078ms   218.9      0.419ms     5.34x +
35B/9B/4B TP1    1024x8              16   32                  0.094ms   181.9      0.426ms     4.51x +
35B/9B/4B TP1    8192x8              16   32                  0.508ms   270.5      3.122ms     6.14x +
35B/9B/4B TP1    8192x16             16   32                  1.057ms   260.0      6.018ms     5.69x +
35B/9B/4B TP1    8192x32             16   32                  2.022ms   271.9     12.009ms     5.94x +

27B TP1          1x65536             16   48                  1.756ms   117.4      5.071ms     2.89x +
27B TP1          1x32768             16   48                  0.897ms   114.9      2.520ms     2.81x +
27B TP1          1x16384             16   48                  0.461ms   111.7      1.274ms     2.76x +
27B TP1          1x8192              16   48                  0.241ms   107.1      0.657ms     2.73x +
27B TP1          1x4096              16   48                  0.130ms    99.0      0.341ms     2.62x +
27B TP1          1x2048              16   48                  0.074ms    87.5      0.189ms     2.56x +
27B TP1          6144+2048           16   48                  0.187ms   138.2      0.597ms     3.20x +
27B TP1          4096+4096           16   48                  0.131ms   196.3      0.660ms     5.03x +
27B TP1          2048+6144           16   48                  0.186ms   138.3      0.664ms     3.56x +
27B TP1          1024+7168           16   48                  0.214ms   120.5      0.666ms     3.11x +
27B TP1          2048x4              16   48                  0.148ms   173.9      0.605ms     4.08x +
27B TP1          1024x8              16   48                  0.139ms   185.1      0.613ms     4.41x +
27B TP1          8192x8              16   48                  0.789ms   261.2      4.573ms     5.79x +
27B TP1          8192x16             16   48                  1.580ms   261.0      8.926ms     5.65x +
27B TP1          8192x32             16   48                  3.119ms   264.4     17.624ms     5.65x +

2B/0.8B TP1      1x65536             16   16                  0.588ms   116.8      2.594ms     4.41x +
2B/0.8B TP1      1x32768             16   16                  0.332ms   103.6      1.303ms     3.93x +
2B/0.8B TP1      1x16384             16   16                  0.199ms    86.5      0.669ms     3.37x +
2B/0.8B TP1      1x8192              16   16                  0.132ms    64.9      0.342ms     2.58x +
2B/0.8B TP1      1x4096              16   16                  0.099ms    43.4      0.178ms     1.80x +
2B/0.8B TP1      1x2048              16   16                  0.078ms    27.4      0.101ms     1.29x +
2B/0.8B TP1      6144+2048           16   16                  0.136ms    63.0      0.294ms     2.16x +
2B/0.8B TP1      4096+4096           16   16                  0.133ms    64.5      0.247ms     1.85x +
2B/0.8B TP1      2048+6144           16   16                  0.136ms    63.2      0.294ms     2.17x +
2B/0.8B TP1      1024+7168           16   16                  0.137ms    62.6      0.319ms     2.32x +
2B/0.8B TP1      2048x4              16   16                  0.075ms   114.3      0.213ms     2.84x +
2B/0.8B TP1      1024x8              16   16                  0.051ms   170.1      0.218ms     4.31x +
2B/0.8B TP1      8192x8              16   16                  0.252ms   272.9      1.555ms     6.18x +
2B/0.8B TP1      8192x16             16   16                  0.534ms   257.2      3.086ms     5.78x +
2B/0.8B TP1      8192x32             16   16                  1.114ms   246.7      5.926ms     5.32x +

Sym h32          1x65536             32   32                  1.170ms   117.5      3.671ms     3.14x +
Sym h32          1x32768             32   32                  0.594ms   115.7      1.826ms     3.08x +
Sym h32          1x16384             32   32                  0.325ms   105.7      0.927ms     2.85x +
Sym h32          1x8192              32   32                  0.192ms    89.6      0.481ms     2.51x +
Sym h32          1x4096              32   32                  0.126ms    68.1      0.249ms     1.97x +
Sym h32          1x2048              32   32                  0.092ms    46.9      0.132ms     1.44x +
Sym h32          6144+2048           32   32                  0.187ms    92.0      0.448ms     2.40x +
Sym h32          4096+4096           32   32                  0.131ms   130.8      0.415ms     3.16x +
Sym h32          2048+6144           32   32                  0.188ms    91.5      0.473ms     2.52x +
Sym h32          1024+7168           32   32                  0.215ms    80.0      0.502ms     2.34x +
Sym h32          2048x4              32   32                  0.079ms   216.1      0.420ms     5.28x +
Sym h32          1024x8              32   32                  0.095ms   180.0      0.426ms     4.46x +
Sym h32          8192x8              32   32                  0.510ms   269.3      3.122ms     6.12x +
Sym h32          8192x16             32   32                  1.120ms   245.5      6.021ms     5.38x +
Sym h32          8192x32             32   32                  2.117ms   259.7     12.018ms     5.68x +

Summary by CodeRabbit

  • New Features

    • Added Blackwell SM100 support for context-parallel Gated Delta Net prefill and delta-rule processing.
    • Added automatic kernel selection, optimized execution, improved chunk sizing, and compiled-kernel reuse.
    • Added optional initial and final state handling, including indexed states and varied state data types.
    • Exposed Blackwell functionality through the public API.
    • Improved device capability detection.
  • Tests

    • Added SM100 coverage for dispatch, end-to-end processing, state handling, and data types.

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📝 Walkthrough

Walkthrough

Adds Blackwell SM100 context-parallel GDN support. The change adds UTCMMA precompute kernels, TCGen05 prefill execution, SM100 dispatch heuristics, optional state handling, public DSL exports, compile-cache support, and architecture-specific tests.

Changes

SM100 context-parallel GDN

Layer / File(s) Summary
SM100 dispatch and chunk heuristics
flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py, flashinfer/gdn_prefill.py, flashinfer/utils.py
Adds SM100 CP eligibility, chunk balancing, device-property caching, indexed-state validation, and architecture-specific dispatch.
SM100 MN precompute kernels
flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py, flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py, flashinfer/gdn_kernels/delta_rule_dsl/alpha.py
Implements UTCMMA precompute, alpha cumulative-product output, TMA and TMEM pipelines, recurrence processing, and launch logic.
SM100 native prefill kernel
flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py
Adds TCGen05 prefill execution with gate preprocessing, recurrent state updates, optional state I/O, TMA pipelines, and output stores.
Pipeline orchestration and exports
flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py, flashinfer/gdn_kernels/__init__.py, flashinfer/gdn_kernels/blackwell/__init__.py, flashinfer/gdn_kernels/delta_rule_dsl/custom_compile_cache.py
Adds SM100 T precompute, fixup, prefill, and top-level entrypoints. It also adds cached compilation lookup and public DSL exports.
Shared state handling
flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_cp_sm90.py, flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_cp_sm120.py
Allows absent final-state outputs and adds optional final-state storage, indexed state mappings, state workspaces, dtype options, and cache-key configuration.
SM100 validation tests
tests/gdn/test_prefill_cp_delta_rule.py, tests/gdn/test_prefill_delta_rule.py
Adds SM100 architecture dispatch, heuristic, MN-kernel, end-to-end, and public-wrapper test coverage.

Estimated code review effort: 5 (Critical) | ~120 minutes

Sequence Diagram(s)

sequenceDiagram
  participant chunk_gated_delta_rule
  participant cp_delta_rule_dsl_sm100
  participant cp_delta_rule_t_precompute_dsl_sm100
  participant cp_delta_rule_mn_precompute_dsl_sm100
  participant cp_delta_rule_fixup_dsl_sm100
  participant cp_delta_rule_prefill_dsl_sm100
  chunk_gated_delta_rule->>cp_delta_rule_dsl_sm100: dispatch SM100 CP workload
  cp_delta_rule_dsl_sm100->>cp_delta_rule_t_precompute_dsl_sm100: compute T workspace
  cp_delta_rule_t_precompute_dsl_sm100->>cp_delta_rule_mn_precompute_dsl_sm100: pass T workspace
  cp_delta_rule_mn_precompute_dsl_sm100->>cp_delta_rule_fixup_dsl_sm100: pass transfer and state workspaces
  cp_delta_rule_fixup_dsl_sm100->>cp_delta_rule_prefill_dsl_sm100: pass fixed state
  cp_delta_rule_prefill_dsl_sm100-->>chunk_gated_delta_rule: write output and optional final state
Loading

Suggested reviewers: bkryu, jiahanc, yzh119

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 15.63% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly identifies the primary change: adding SM100 context-parallel delta-rule prefill support.
Description check ✅ Passed The description includes all required sections, a related issue, completed checklists, test information, and detailed benchmark results.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
✨ Finishing Touches 💡 1
📝 Generate docstrings 💡
  • Create stacked PR
  • Commit on current branch
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Commit unit tests in branch cp_delta_rule_sm100

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Code Review

This pull request adds native context-parallel (CP) Gated Delta Net (GDN) prefill kernels for Blackwell SM100 GPUs, including MN precompute, state fixup, and prefill DSL implementations, along with corresponding dispatch heuristics and end-to-end tests. The review feedback identifies a potential division-by-zero error in the dispatch heuristics when the number of sequences is zero, and suggests optimizing GPU memory usage by deferring the allocation of tensormaps_t to the reference kernel path instead of allocating it unconditionally.

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Comment thread flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py Outdated
Comment thread flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py Outdated
Comment thread flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py Outdated
@guangyunh-nv
guangyunh-nv force-pushed the cp_delta_rule_sm100 branch from 22d584c to 963fbf9 Compare July 22, 2026 03:28
@guangyunh-nv
guangyunh-nv marked this pull request as ready for review July 22, 2026 03:28
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Actionable comments posted: 1

🧹 Nitpick comments (1)
flashinfer/gdn_prefill.py (1)

317-324: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick win

Update the use_cp docstring to include SM100.

This change enables CP dispatch for _arch_major == 10, but the use_cp parameter docstring (lines 196-200) still reads "SM90/SM120 context-parallel DSL implementation." Please sync it to mention SM100. As per coding guidelines: "Keep documentation in sync with code changes."

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_prefill.py` around lines 317 - 324, Update the use_cp
parameter docstring to mention SM100 alongside SM90 and SM120, keeping the
documentation aligned with the _arch_major support in the cp_heuristic_matches
logic.

Source: Coding guidelines

🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@flashinfer/gdn_prefill.py`:
- Around line 63-73: Update _cp_delta_rule_rejection_reason to reject non-fp32
initial_state when arch_major is 10, returning a rejection reason so auto
routing falls back to the non-CP path. Preserve the existing SM100
kernel-availability and other architecture checks.

---

Nitpick comments:
In `@flashinfer/gdn_prefill.py`:
- Around line 317-324: Update the use_cp parameter docstring to mention SM100
alongside SM90 and SM120, keeping the documentation aligned with the _arch_major
support in the cp_heuristic_matches logic.
🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

  • Push a commit to this branch (recommended)
  • Create a new PR with the fixes

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 40b2faf3-6882-4d90-8d05-2adb6c0e131d

📥 Commits

Reviewing files that changed from the base of the PR and between b7cd951 and 963fbf9.

📒 Files selected for processing (8)
  • flashinfer/gdn_kernels/__init__.py
  • flashinfer/gdn_kernels/blackwell/__init__.py
  • flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py
  • flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py
  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py
  • flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
  • flashinfer/gdn_prefill.py
  • tests/gdn/test_prefill_cp_delta_rule.py

Comment thread flashinfer/gdn_prefill.py
@kahyunnam

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/bot run tests/gdn

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GitLab MR !1030 has been created, and the CI pipeline #59316121 is currently running. I'll report back once the pipeline job completes.

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[FAILED] Pipeline #59316121 — 11/18 executed test jobs passed

Compared with nightly #59054944 (different CI configuration).

Unit Tests

GPU CUDA 12.9 CUDA 13.0 Notes
5090 ✅ Pass ✅ Pass
B300 ❌ New ✅ Pass PR-related: tests.gdn.test_prefill_cp_delta_rule (89 failures; CUDA 12.9)
GB200 ❔ Unknown ❔ Unknown Unknown: script failed before producing a JUnit report (2 jobs; CUDA 12.9, CUDA 13.0)
GB300 ❔ Unknown ❔ Unknown Not compared: tests.gdn.test_prefill_cp_delta_rule (90 failures; CUDA 12.9, CUDA 13.0)
H100 ✅ Pass ✅ Pass
RTX Pro 6000 Blackwell ✅ Pass ✅ Pass

✅ Pass · 🟡 Old failure · ❌ New failure · ⏱ Test timeout · ⚠️ Infrastructure · ❔ Unknown or unclassified · — Not run

Multi-GPU and Multi-Node Tests — 4/6 passed

GPU CUDA 12.9 CUDA 13.0 Notes
B300 (multi-GPU) ✅ Pass ✅ Pass
GB200 (multi-node) ❔ Failed ❔ Failed
GB300 (multi-node) ✅ Pass ✅ Pass
Failure details

PR-related regressions

  • tests.gdn.test_prefill_cp_delta_rule — 89 failures on B300 / CUDA 12.9
    • NotImplementedError: Blackwell GDN prefill is only supported on CUDA 13+

Could not compare

  • tests.gdn.test_prefill_cp_delta_rule — 90 failures on GB300 / CUDA 12.9, GB300 / CUDA 13.0
    • NotImplementedError: Blackwell GDN prefill is only supported on CUDA 13+

Timeouts, infrastructure, or incomplete jobs

  • Unknown: script failed before producing a JUnit report — GB200 / CUDA 12.9, GB200 / CUDA 13.0
    • Jobs: unit_test_gb200: [cu130], unit_test_gb200: [cu129]

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Actionable comments posted: 5

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (2)
flashinfer/gdn_prefill.py (2)

363-372: 📐 Maintainability & Code Quality | 🟡 Minor | ⚡ Quick win

Update the state-index dispatch documentation.

The comment and error text state that state_indices is supported only by the non-CP SM100 kernel. The code now forwards state_indices to cp_delta_rule_dsl_sm100.

Describe support as SM100/SM103-specific without excluding CP.

As per coding guidelines, keep documentation synchronized with code changes. <coding_guidelines>

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_prefill.py` around lines 363 - 372, Update the documentation
and NotImplementedError text in the state_indices dispatch guard to describe
support as SM100/SM103-specific without saying it is non-CP-only. Keep the
validation logic unchanged, including the _arch_major check and existing use_cp
context.

Source: Coding guidelines


437-449: 🎯 Functional Correctness | 🟠 Major | ⚡ Quick win

Convert cu_seqlens for the selected CP architecture.

The public API accepts either integer dtype. This call now forwards the tensor unchanged. SM90 and SM120 CP wrappers require torch.int64, while SM100 accepts its supported index dtypes. An int32 input therefore fails only when automatic routing selects SM90 or SM120 CP.

Convert to int64 for SM90 and SM120, or make all selected kernels accept the documented input dtypes.

Proposed fix
+            cp_cu_seqlens = (
+                cu_seqlens if _arch_major == 10 else cu_seqlens.to(torch.int64)
+            )
             cp_delta_rule_dsl(
                 output,
                 output_state,
                 q,
                 k,
                 v,
                 _g,
                 _beta,
-                cu_seqlens,
+                cp_cu_seqlens,
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_prefill.py` around lines 437 - 449, Update the
cp_delta_rule_dsl invocation in the CP prefill path to convert cu_seqlens to
torch.int64 when routing to SM90 or SM120 architectures, while preserving
supported input dtypes for SM100. Ensure both documented integer input dtypes
work with automatic CP architecture selection.
🧹 Nitpick comments (9)
flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py (3)

1691-1691: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low value

Delete the two dead locals.

valid_tokens at line 1691 and sum_v at line 1713 are assigned and never read. Both carry # noqa: F841 to silence the linter. Remove the assignments and the suppressions instead of keeping them.

Also applies to: 1713-1713

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py` at line 1691,
Remove the unused valid_tokens assignment near batch_end and the unused sum_v
assignment in the same function, including their # noqa: F841 suppressions.
Leave the surrounding computation unchanged.

Source: Linters/SAST tools


1737-1743: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low value

Drop the unused work_args and unused unpacked names.

mma_cg0_warp declares work_args and never reads it; mma_cg0_pair_cp passes an empty tuple at line 2005. Static analysis also reports unused unpacked names at lines 2061 (tiled_mma_kv), 2065 (batch_idx), 2474 (sV), 2687 (sBeta), and 2703 (num_pairs_b). Remove the parameter and prefix the intentionally unused names with an underscore.

Also applies to: 2035-2043

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py` around lines
1737 - 1743, Remove the unused work_args parameter from mma_cg0_warp and stop
passing the empty tuple from mma_cg0_pair_cp. Rename the intentionally unused
unpacked names at the referenced sites—tiled_mma_kv, batch_idx, sV, sBeta, and
num_pairs_b—with an underscore prefix while preserving tuple unpacking behavior.

Source: Linters/SAST tools


2431-2444: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚖️ Poor tradeoff

The checkpoint blocks are unreachable in this class.

__init__ pins self.enable_checkpoints = False at line 195 and ignores the enable_checkpoints argument. Every guarded block therefore compiles out, and mS_checkpoints, checkpoint_offset, and checkpoint_every_n_tokens thread dead values through compute_group_1_chunk and _store_final_state. If CP will never support checkpointing, remove the parameter and the blocks. If it will, add a TODO that states the intent.

Also applies to: 2953-2994

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py` around lines
2431 - 2444, Update the class initialization and checkpoint flow so checkpoint
support is explicit: either honor the constructor’s enable_checkpoints argument
and ensure the checkpoint values reach compute_group_1_chunk and
_store_final_state, or, if CP will not support checkpoints, remove the
parameter, guarded checkpoint blocks, and dead mS_checkpoints,
checkpoint_offset, and checkpoint_every_n_tokens plumbing; if retaining the
disabled path, add a TODO documenting the intended support.
flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py (3)

906-910: 🚀 Performance & Scalability | 🔵 Trivial | 💤 Low value

Remove the duplicate TMEM store fence.

_scale_tmem_matrix already ends with cute.arch.fence_view_async_tmem_store() at line 292. The fence at line 909 repeats it with no intervening TMEM store. Drop it unless it guards a hazard that is not visible here.

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py` around lines 906 -
910, Remove the redundant cute.arch.fence_view_async_tmem_store() call
immediately after _scale_tmem_matrix in the update path, since
_scale_tmem_matrix already fences its TMEM store. Keep
y_ready_producer.acquire_and_advance().commit() and the surrounding
synchronization unchanged.

1365-1365: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low value

Use the named warp-ID attributes in this dispatch condition.

Every other branch in this dispatch chain compares warp_idx against a named attribute, for example self.transfer_mma_warp_id and self.compute_group_1_warp_ids. This branch hardcodes 0 and 3. If compute_group_0_warp_ids changes, this branch silently diverges.

♻️ Proposed change
-        elif is_valid_chunk and warp_idx >= 0 and warp_idx <= 3:
+        elif (
+            is_valid_chunk
+            and warp_idx >= self.compute_group_0_warp_ids[0]
+            and warp_idx <= self.compute_group_0_warp_ids[-1]
+        ):
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py` at line 1365, Update
the dispatch condition in the branch following the `is_valid_chunk` check to
compare `warp_idx` against the bounds represented by
`self.compute_group_0_warp_ids` instead of hardcoded `0` and `3`. Preserve the
existing validity and inclusive range behavior while deriving both limits from
the named attribute.

851-857: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low value

Rename the tiled_mma_z parameter of run_compute_group_1.

The caller at line 1399 passes tiled_mma_y into this slot. The parameter name states z. Rename the parameter to tiled_mma_y so the reader does not have to trace the call site to learn which MMA is used.

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py` around lines 851 -
857, Rename the run_compute_group_1 parameter tiled_mma_z to tiled_mma_y,
preserving its position and behavior so it matches the tiled_mma_y value passed
by the caller.
flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py (2)

156-158: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick win

Extract the duplicated from_dlpack lambda into one module-level helper. All four wrappers define the identical from_dlpack lambda inside their compile branch. Ruff reports E731 at each site. One shared def at module scope removes the duplication and clears all four findings.

  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py#L156-L158: delete the local lambda in cp_delta_rule_t_precompute_dsl_sm100 and call the shared helper.
  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py#L311-L313: delete the local lambda in cp_delta_rule_mn_precompute_dsl_sm100 and call the shared helper.
  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py#L563-L565: delete the local lambda in cp_delta_rule_fixup_dsl_sm100 and call the shared helper.
  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py#L841-L843: delete the local lambda in cp_delta_rule_prefill_dsl_sm100 and call the shared helper.
♻️ Proposed helper

Add near _get_cp_workspace:

def _from_dlpack(*args, **kwargs):
    return cute.runtime.from_dlpack(*args, **{**kwargs, "enable_tvm_ffi": True})

Then at each site:

-        from_dlpack = lambda *args, **kwargs: cute.runtime.from_dlpack(
-            *args, **{**kwargs, "enable_tvm_ffi": True}
-        )
+        from_dlpack = _from_dlpack
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py` around lines 156 - 158,
Extract the duplicated from_dlpack lambda into a single module-level
_from_dlpack helper near _get_cp_workspace, preserving the enable_tvm_ffi
behavior. Remove the local lambda and use the shared helper in
cp_delta_rule_t_precompute_dsl_sm100 at
flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py:156-158,
cp_delta_rule_mn_precompute_dsl_sm100 at :311-313, cp_delta_rule_fixup_dsl_sm100
at :563-565, and cp_delta_rule_prefill_dsl_sm100 at :841-843.

Source: Linters/SAST tools


538-550: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low value

Avoid exposing unsupported SM100 fixup kernel kinds.

cp_delta_rule_fixup_dsl_sm100() auto-selects only simt_row4, utcmma64, and utcmma128, but _get_fixup_kernel() also accepts simt_row8 and hmma. Those branches can only be reached by passing an unsupported _kernel_kind manually. Remove the unsupported branches or add SM100 selection paths/tests for them.

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py` around lines 538 - 550,
Update _get_fixup_kernel() to stop accepting the unsupported simt_row8 and hmma
kernel kinds for cp_delta_rule_fixup_dsl_sm100(); remove those branches so
dispatch is limited to the three kinds selected by
cp_delta_rule_fixup_dsl_sm100(): simt_row4, utcmma64, and utcmma128.
flashinfer/utils.py (1)

281-282: 🚀 Performance & Scalability | 🔵 Trivial | ⚡ Quick win

Cache the shared device-property lookup.

get_device_properties is not decorated with functools.cache. As a result, get_device_sm_count and other direct consumers still query CUDA properties on each call.

Proposed fix
+@functools.cache
 def get_device_properties(device: torch.device):
     return torch.cuda.get_device_properties(device)
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/utils.py` around lines 281 - 282, Decorate get_device_properties
with functools.cache so repeated lookups for the same device reuse the cached
CUDA properties. Import functools as needed, while leaving get_device_sm_count
and other consumers unchanged.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py`:
- Around line 2590-2609: Resolve the redundant `valid_state` branch in the
`num_kphases_qkv` GEMM loop: determine the intended accumulation seed by
matching the sibling GEMM loops, using `valid_state or (kphase_idx != 0)` if the
non-initial-state path requires accumulation from later phases; otherwise
collapse both identical branches into one loop. Ensure the resulting behavior
remains correct if `valid_state` becomes false in the future.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py`:
- Around line 1533-1565: Run ruff format on the file, allowing it to normalize
the column-aligned assignments in CPDeltaRuleFixupUtcmmaSm100.__init__ and the
compressed signatures below it. Commit the formatter’s complete output without
manual formatting overrides.

In `@flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py`:
- Line 817: Run ruff format on
flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py and commit the resulting
formatting changes, including wrapping the state_dtype ternary chain and the
nearby multi-condition checks to match Ruff’s output.

In `@flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py`:
- Around line 150-169: Update the calls to the chunk-length heuristic in
cp_delta_rule_dsl_sm90 and cp_delta_rule_dsl_sm120 to pass each caller’s actual
num_seqs value along with total_seqlen. Preserve the existing heuristic logic in
chunk_bound_for_len and ensure both SM90 and SM120 paths no longer rely on the
default num_seqs=1.

In `@flashinfer/gdn_prefill.py`:
- Around line 353-362: Update the CP dispatch decision around
_cp_delta_rule_rejection_reason to reject SM100 CP when the CUDA version is
below 13, before will_use_cp can select it. For use_cp == "auto", return the
non-CP path when this rejection applies; preserve explicit use_cp=True rejection
behavior and existing supported-version dispatch.

---

Outside diff comments:
In `@flashinfer/gdn_prefill.py`:
- Around line 363-372: Update the documentation and NotImplementedError text in
the state_indices dispatch guard to describe support as SM100/SM103-specific
without saying it is non-CP-only. Keep the validation logic unchanged, including
the _arch_major check and existing use_cp context.
- Around line 437-449: Update the cp_delta_rule_dsl invocation in the CP prefill
path to convert cu_seqlens to torch.int64 when routing to SM90 or SM120
architectures, while preserving supported input dtypes for SM100. Ensure both
documented integer input dtypes work with automatic CP architecture selection.

---

Nitpick comments:
In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py`:
- Line 1691: Remove the unused valid_tokens assignment near batch_end and the
unused sum_v assignment in the same function, including their # noqa: F841
suppressions. Leave the surrounding computation unchanged.
- Around line 1737-1743: Remove the unused work_args parameter from mma_cg0_warp
and stop passing the empty tuple from mma_cg0_pair_cp. Rename the intentionally
unused unpacked names at the referenced sites—tiled_mma_kv, batch_idx, sV,
sBeta, and num_pairs_b—with an underscore prefix while preserving tuple
unpacking behavior.
- Around line 2431-2444: Update the class initialization and checkpoint flow so
checkpoint support is explicit: either honor the constructor’s
enable_checkpoints argument and ensure the checkpoint values reach
compute_group_1_chunk and _store_final_state, or, if CP will not support
checkpoints, remove the parameter, guarded checkpoint blocks, and dead
mS_checkpoints, checkpoint_offset, and checkpoint_every_n_tokens plumbing; if
retaining the disabled path, add a TODO documenting the intended support.

In `@flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py`:
- Around line 906-910: Remove the redundant
cute.arch.fence_view_async_tmem_store() call immediately after
_scale_tmem_matrix in the update path, since _scale_tmem_matrix already fences
its TMEM store. Keep y_ready_producer.acquire_and_advance().commit() and the
surrounding synchronization unchanged.
- Line 1365: Update the dispatch condition in the branch following the
`is_valid_chunk` check to compare `warp_idx` against the bounds represented by
`self.compute_group_0_warp_ids` instead of hardcoded `0` and `3`. Preserve the
existing validity and inclusive range behavior while deriving both limits from
the named attribute.
- Around line 851-857: Rename the run_compute_group_1 parameter tiled_mma_z to
tiled_mma_y, preserving its position and behavior so it matches the tiled_mma_y
value passed by the caller.

In `@flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py`:
- Around line 156-158: Extract the duplicated from_dlpack lambda into a single
module-level _from_dlpack helper near _get_cp_workspace, preserving the
enable_tvm_ffi behavior. Remove the local lambda and use the shared helper in
cp_delta_rule_t_precompute_dsl_sm100 at
flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py:156-158,
cp_delta_rule_mn_precompute_dsl_sm100 at :311-313, cp_delta_rule_fixup_dsl_sm100
at :563-565, and cp_delta_rule_prefill_dsl_sm100 at :841-843.
- Around line 538-550: Update _get_fixup_kernel() to stop accepting the
unsupported simt_row8 and hmma kernel kinds for cp_delta_rule_fixup_dsl_sm100();
remove those branches so dispatch is limited to the three kinds selected by
cp_delta_rule_fixup_dsl_sm100(): simt_row4, utcmma64, and utcmma128.

In `@flashinfer/utils.py`:
- Around line 281-282: Decorate get_device_properties with functools.cache so
repeated lookups for the same device reuse the cached CUDA properties. Import
functools as needed, while leaving get_device_sm_count and other consumers
unchanged.
🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

  • Push a commit to this branch (recommended)
  • Create a new PR with the fixes

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro Plus

Run ID: 2515ecef-f5ba-4323-bf4d-bf531cd78893

📥 Commits

Reviewing files that changed from the base of the PR and between 963fbf9 and bb694ec.

📒 Files selected for processing (12)
  • flashinfer/gdn_kernels/__init__.py
  • flashinfer/gdn_kernels/blackwell/__init__.py
  • flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py
  • flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py
  • flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py
  • flashinfer/gdn_kernels/delta_rule_dsl/alpha.py
  • flashinfer/gdn_kernels/delta_rule_dsl/custom_compile_cache.py
  • flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_cp_sm120.py
  • flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_cp_sm90.py
  • flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
  • flashinfer/gdn_prefill.py
  • flashinfer/utils.py
🚧 Files skipped from review as they are similar to previous changes (2)
  • flashinfer/gdn_kernels/blackwell/init.py
  • flashinfer/gdn_kernels/init.py

Comment thread flashinfer/gdn_kernels/blackwell/gated_delta_net_cp_prefill.py Outdated
Comment thread flashinfer/gdn_kernels/blackwell/gated_delta_net_cp.py Outdated
Comment thread flashinfer/gdn_kernels/blackwell/gdn_cp_prefill.py Outdated
Comment on lines +150 to +169
# Target one wave of MN CTAs. Account for the known longest sequence, then
# safely bound the chunks contributed by all remaining uneven sequences.
target_chunks = max(1, num_sms // num_heads)
min_chunk_len = _ceil_div(max_seqlen, target_chunks)
return _round_up(min_chunk_len, chunk_len_granularity)
remaining_seqlen = max(0, total_seqlen - max_seqlen)
remaining_seqs = max(0, num_seqs - 1)

def chunk_bound_for_len(chunk_len: int) -> int:
return _ceil_div(max_seqlen, chunk_len) + chunk_bound_host(
remaining_seqs, remaining_seqlen, chunk_len
)

lo = 1
hi = max(1, _ceil_div(max_seqlen, chunk_len_granularity))
while lo < hi:
mid = (lo + hi) // 2
if chunk_bound_for_len(mid * chunk_len_granularity) <= target_chunks:
hi = mid
else:
lo = mid + 1
return lo * chunk_len_granularity

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🚀 Performance & Scalability | 🟠 Major | ⚡ Quick win

Pass num_seqs from the SM90 and SM120 callers.

Those callers provide total_seqlen but retain the default num_seqs=1. Therefore, remaining_seqs becomes zero and chunk_bound_host ignores the per-sequence ceiling cost. The heuristic can select a chunk length that launches more than the target one-wave CTA count.

Pass the actual sequence count from cp_delta_rule_dsl_sm90 and cp_delta_rule_dsl_sm120.

🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py` around lines 150 -
169, Update the calls to the chunk-length heuristic in cp_delta_rule_dsl_sm90
and cp_delta_rule_dsl_sm120 to pass each caller’s actual num_seqs value along
with total_seqlen. Preserve the existing heuristic logic in chunk_bound_for_len
and ensure both SM90 and SM120 paths no longer rely on the default num_seqs=1.

Comment thread flashinfer/gdn_prefill.py

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Actionable comments posted: 1

🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@tests/gdn/test_prefill_cp_delta_rule.py`:
- Line 89: Update the CUDA-version skip diagnostics to use consistent
SM100/SM103 (or SM10x) wording: change the message in
tests/gdn/test_prefill_cp_delta_rule.py at lines 89-89 and apply the same
wording in tests/gdn/test_prefill_delta_rule.py at lines 58-58, preserving the
existing CUDA version details.
🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

  • Push a commit to this branch (recommended)
  • Create a new PR with the fixes

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro Plus

Run ID: 4e1d618f-3075-495e-8231-424635f56d7e

📥 Commits

Reviewing files that changed from the base of the PR and between bb694ec and 66c515d.

📒 Files selected for processing (2)
  • tests/gdn/test_prefill_cp_delta_rule.py
  • tests/gdn/test_prefill_delta_rule.py

Comment thread tests/gdn/test_prefill_cp_delta_rule.py
@jiahanc

jiahanc commented Aug 4, 2026

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/bot run tests/gdn

@flashinfer-bot

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GitLab MR !1030 has been updated with latest changes, and the CI pipeline #60988907 is currently running. I'll report back once the pipeline job completes.

@flashinfer-bot

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[FAILED] Pipeline #60988907 — 17/18 executed test jobs passed

Compared with nightly #60831563.

Unit Tests

GPU CUDA 12.9 CUDA 13.0 Notes
5090 ✅ Pass ✅ Pass
B300 ✅ Pass ✅ Pass
GB200 ✅ Pass ✅ Pass
GB300 ✅ Pass ✅ Pass
H100 ✅ Pass ✅ Pass
RTX Pro 6000 Blackwell ✅ Pass ✅ Pass

✅ Pass · 🟡 Old failure · ❌ New failure · ⏱ Test timeout · ⚠️ Infrastructure · ❔ Unknown or unclassified · — Not run

Multi-GPU and Multi-Node Tests — 5/6 passed

GPU CUDA 12.9 CUDA 13.0 Notes
B300 (multi-GPU) ❔ Failed ✅ Pass
GB200 (multi-node) ✅ Pass ✅ Pass
GB300 (multi-node) ✅ Pass ✅ Pass

No individual test or infrastructure failures could be extracted.

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Thanks for the contribution!

@jiahanc
jiahanc merged commit 7dce283 into main Aug 5, 2026
56 of 62 checks passed
@jiahanc
jiahanc deleted the cp_delta_rule_sm100 branch August 5, 2026 06:09
@vadiklyutiy

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@guangyunh-nv
Is there a chance that you have comparison of new CP kernel vs current FI's GDN kernel?

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@yzh119 @yyihuang Please restore old PR description. You should not edit a merged PR!

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yzh119 commented Aug 17, 2026

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Hi @guangyunh-nv thanks for the reminder and this should never happen again, I have made some changes on the github side and agent side to prohibit such behaviors.

kahyunnam added a commit that referenced this pull request Aug 19, 2026
Mirrors the v0.6.16 revert (#4246, commit 0a27ba3) and its v0.6.17
counterpart (09fd5fc) so that 0.6.18 does not ship the API-breaking
ring-buffer cache contract that neither 0.6.16 nor 0.6.17 shipped.
Reverts:

  afd4754  mamba checkpointing SSU: two-kernel split + ring-buffer
            cache for checkpointing SSU (#3975)
  f90e9c4  docs(mamba): document checkpointing varlen arguments (#4129)

Like release-v0.6.17, this branch carries #4129 as well, so both are
reverted; 0.6.16 only needed #3975. main still carries both.

Verified no collateral damage: the SM107 change from #4280 in
tests/mamba/conftest.py and the #4029/#4078 changes in
flashinfer/utils.py are preserved, and the five core reverted files now
byte-match release-v0.6.17.

NOTE: like both earlier reverts, this also reverts the cvt_rs fix that
rode along in #3975 -- is_cvt_rs_supported goes back to
`major in (10, 11)` (wrong for SM110a) and the CUDA guard back to
SM100_ALL only (B300/sm_103a falls to software emulation). That matches
what 0.6.17 shipped, but the hunk remains a candidate to keep.
@kahyunnam kahyunnam added model: qwen3.5 / 3.6 / 3.8 op: linear attention KDA, mamba, GDN, etc. review filtering. labels Sep 2, 2026
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6 participants