Fix 10 bugs in BF16 XQA MLA kernel for SM120/SM121#2689
Fix 10 bugs in BF16 XQA MLA kernel for SM120/SM121#2689blake-snc wants to merge 8 commits intoflashinfer-ai:mainfrom
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Validated on SM121a (DGX Spark GB10). The original PR flashinfer-ai#2675 kernel produces 100% NaN output for BF16. These fixes make it fully correct (max_diff < 11 microunits vs PyTorch reference across batch sizes 1/2/4, seq lengths 128/256/512/1024). Bugs fixed: 1. Missing MLA_BF16 preprocessor flag in defines.h — BF16 MLA was compiling with FP8 INPUT_ELEM types, causing type mismatches throughout the kernel. 2. FP8-only JIT assertions in jit/xqa.py — gen_xqa_module_mla() asserted input_dtype == fp8, blocking BF16 compilation entirely. Added bf16 to allowed dtypes and set -DMLA_BF16=1 flag. 3. Q tensor map hardcoded 64B swizzle — partElemsK=64 with 2-byte BF16 = 128 bytes per partition, requiring 128B swizzle. Made swizzle dynamic based on partBytes. 4. V tensor map 256-byte box exceeds max swizzle — partElemsV=128 with BF16 = 256 bytes, but max TMA swizzle is 128B. Reduced partElemsV to 64 for BF16 (128 bytes, matches 128B swizzle). 5. Consumer .b8 ldmatrix transpose scrambles BF16 — ldmatrix_16x16_trans uses .b8 which byte-transposes, scrambling 2-byte BF16 values. Replaced with ldmatrix<true, 2> (.b16 transpose) for BF16 path. 6. Consumer OOB access rows 16-47 in 32-row buffer — FP8 has tokensPerTile=64 but BF16 has tokensPerTile=32. The consumer V loading iterated over 48 rows (warpTileNbAtomBx2=3), accessing rows beyond the 32-row buffer. Restructured BF16 consumer to iterate over V parts within the 32-row tile. 7. V buffer 4-part layout incompatible with single-part consumer — FP8 uses partElemsV=128 (4 parts per V head), but BF16 needs partElemsV=64 to fit swizzle. Adjusted V splitting to match. 8. Register pressure causes stack overflow crash — BF16 doubles register usage vs FP8 for Q cache. Reduced buffer counts to stay within register budget. 9. storeOrderedXToShmBf16 OOB WarpAcc indexing — original implementation indexed WarpAcc as src(row/2, col/2)(row%2, col%2) which doesn't match MMA accumulator layout. Rewrote to use correct MMA register mapping: src(instM, instN)(iM, iN) at row=instM*16+lane/4+iM*8. 10. Q register prefetch idxAtomBx2==2 never triggers for BF16 — the GEMM0 inner loop prefetches Q registers at idxAtomBx2==2, but BF16 has tileNbAtomBx2=2 (range 0..1), so the condition never fires. regQBuf[1..3] stay uninitialized → garbage GEMM0 → NaN softmax → NaN output. Fixed with constexpr qPrefetchAtomBx2 = min(2, tileNbAtomBx2-1). Validation results on SM121a (DGX Spark): B=1 seq=128: PASS, max_diff=0.000011, NaN=0 B=1 seq=256: PASS, max_diff=0.000006, NaN=0 B=1 seq=512: PASS, max_diff=0.000005, NaN=0 B=1 seq=1024: PASS, max_diff=0.000004, NaN=0 B=2 seq=128: PASS, max_diff=0.000011, NaN=0 B=2 seq=256: PASS, max_diff=0.000007, NaN=0 B=4 seq=128: PASS, max_diff=0.000010, NaN=0 B=4 seq=1024: PASS, max_diff=0.000005, NaN=0 Contributed by Second Nature Computing (https://joinsecondnature.com) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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📝 WalkthroughWalkthroughAdds BF16 (bfloat16) support to the MLA XQA backend: build/runtime dtype branching for BF16 vs FP8, BF16-aware QMMA shapes and shared-memory sizing, BF16-specific load/store/prefetch paths and swizzle selection, JIT/python flag and validation updates, and improved KV-cache partition error messaging. Changes
Sequence Diagram(s)sequenceDiagram
participant User as User/API
participant Python as flashinfer/jit & mla.py
participant NVCC as JIT compiler (nvcc)
participant Host as Host launcher (configureKernel)
participant Device as CUDA Kernel (mla_sm120)
User->>Python: request XQA MLA module (input_dtype, kv_cache_dtype)
Python->>Python: validate dtype pair & SM12x support
Python->>NVCC: generate compile flags (MLA_BF16? CACHE_ELEM_ENUM)
NVCC-->>Python: compiled module
Host->>Host: configureKernel() (set smem limits, validate)
Host->>Device: launch kernel with kernelQmmaShape & smem
Device->>Device: select MathElem path (BF16 or FP8), prefetch/load/store
Device-->>Host: output/results
Host-->>User: deliver inference outputs
Estimated code review effort🎯 4 (Complex) | ⏱️ ~45 minutes Possibly related issues
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Summary of ChangesHello, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request addresses and resolves ten critical bugs in the BF16 XQA MLA kernel for SM120/SM121 architectures, which previously caused 100% NaN output. The changes enable functional BF16 support by correctly configuring data types, memory access patterns, and kernel parameters, ensuring accurate results with minimal differences compared to PyTorch references. Highlights
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Code Review
This pull request provides a comprehensive set of fixes for the BF16 XQA MLA kernel, addressing 10 distinct bugs that caused NaN outputs. The changes span from CUDA kernel logic and memory management to Python JIT compilation flags, demonstrating a deep understanding of the hardware and software stack. The fixes appear correct and are well-documented in the pull request description. My review includes a few suggestions to improve code clarity and maintainability by simplifying some conditional expressions and refactoring duplicated code.
csrc/xqa/mla_sm120.cu
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| inline constexpr bool is_fp8 = (mathElemBytes == 1); | ||
| inline constexpr bool is_bf16 = (mathElemBytes == 2); | ||
| // BF16: partElemsK=64, nbKBufs=2 → ~100KB, under 99KB opt-in (101376). | ||
| inline constexpr uint32_t partElemsK = is_fp8 ? 64 : is_bf16 ? 64 : 64; |
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The ternary expression for partElemsK is a bit confusing as it evaluates to 64 for all supported cases (is_fp8 or is_bf16). It can be simplified to a direct assignment for better readability.
inline constexpr uint32_t partElemsK = 64;
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Fixed in fc43222 — simplified to direct assignment / two-branch ternary.
csrc/xqa/mla_sm120.cu
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|
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| inline constexpr uint32_t tokensPerTile = 64; | ||
| inline constexpr uint32_t partElemsV = 128; | ||
| inline constexpr uint32_t tokensPerTile = is_fp8 ? 64 : is_bf16 ? 32 : 64; |
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The ternary expression for tokensPerTile has an unreachable fallback case. Since is_fp8 and is_bf16 are mutually exclusive for the supported data types in this kernel, the expression can be simplified to improve clarity.
inline constexpr uint32_t tokensPerTile = is_fp8 ? 64 : 32;
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Fixed in fc43222 — simplified to direct assignment / two-branch ternary.
csrc/xqa/mla_sm120.cu
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| static inline constexpr uint32_t nbKBufs = 12; | ||
| // BF16: 2 K-buffers to fit ≤99KB opt-in (~100096 bytes); 3 buffers would need ~104KB (128KB | ||
| // arch). | ||
| static inline constexpr uint32_t nbKBufs = is_fp8 ? 12 : (is_bf16 ? 2 : 12); |
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The ternary expression for nbKBufs has an unreachable fallback case. Since is_fp8 and is_bf16 are mutually exclusive for the supported data types in this kernel, the expression can be simplified for better readability.
static inline constexpr uint32_t nbKBufs = is_fp8 ? 12 : 2;
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Fixed in fc43222 — simplified to direct assignment / two-branch ternary.
| uint32_t size; | ||
| cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize)); | ||
| cudaFuncSetAttribute(kernel_mha, cudaFuncAttributeMaxDynamicSharedMemorySize, size); | ||
| checkCuda(cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize))); | ||
| int devMaxShmem = 0; | ||
| checkCuda(cudaDeviceGetAttribute(&devMaxShmem, cudaDevAttrMaxSharedMemoryPerBlockOptin, 0)); | ||
| if (size > (uint32_t)devMaxShmem) { | ||
| throw std::runtime_error("XQA MLA kernel requires " + std::to_string(size) + | ||
| " bytes shared memory per block, but " | ||
| "device opt-in max is " + | ||
| std::to_string(devMaxShmem) + ". BF16 MLA needs 128 KB (e.g. SM12x)."); | ||
| } | ||
| checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributePreferredSharedMemoryCarveout, | ||
| cudaSharedmemCarveoutMaxShared)); | ||
| checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributeMaxDynamicSharedMemorySize, size)); | ||
| return size; | ||
| } |
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This block of code for configuring shared memory is nearly identical to the lambda function used to initialize hostSmemSize in launchMLA (lines 1763-1779). To improve maintainability and reduce duplication, consider extracting this logic into a helper function that can be called from both places.
For example:
static uint32_t configureKernelSharedMemory() {
uint32_t size;
checkCuda(cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize)));
int devMaxShmem = 0;
checkCuda(cudaDeviceGetAttribute(&devMaxShmem, cudaDevAttrMaxSharedMemoryPerBlockOptin, 0));
if (size > (uint32_t)devMaxShmem) {
throw std::runtime_error("XQA MLA kernel requires " + std::to_string(size) +
" bytes shared memory per block, but "
"device opt-in max is " +
std::to_string(devMaxShmem) + ". BF16 MLA needs 128 KB (e.g. SM12x).");
}
checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributePreferredSharedMemoryCarveout,
cudaSharedmemCarveoutMaxShared));
checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributeMaxDynamicSharedMemorySize, size));
return size;
}Then both launchMLA and configureKernel can use this helper.
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Fixed in fc43222 — launchMLA now calls configureKernel() instead of duplicating the logic.
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Actionable comments posted: 1
🧹 Nitpick comments (2)
csrc/xqa/mla_sm120.cu (2)
1733-1734: Swizzle selection correctly handles BF16.The calculation
partBytes = partElems * elemByteswith conditional swizzle selection addresses PR bug#3(Q tensor map hardcoded 64B swizzle). BF16 (64 elements × 2 bytes = 128B) correctly getsCU_TENSOR_MAP_SWIZZLE_128B.Consider adding a fallback error path for unsupported
partBytesvalues, similar tomakeTensorMapForPagedKVCachein tensorMap.cpp, to catch configuration errors at runtime rather than silently using 64B swizzle.Optional: Add explicit error handling
uint32_t const partBytes = partElems * elemBytes; - auto const swizzle = (partBytes == 128) ? CU_TENSOR_MAP_SWIZZLE_128B : CU_TENSOR_MAP_SWIZZLE_64B; + auto const swizzle = [&] { + switch (partBytes) { + case 128: + return CU_TENSOR_MAP_SWIZZLE_128B; + case 64: + return CU_TENSOR_MAP_SWIZZLE_64B; + default: + throw std::runtime_error("unsupported Q partition size: " + std::to_string(partBytes) + + " bytes (partElems=" + std::to_string(partElems) + + ", elemBytes=" + std::to_string(elemBytes) + ")"); + } + }();🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` around lines 1733 - 1734, The swizzle selection should not silently fall back to 64B for unexpected partBytes; update the code around partBytes/partElems/elemBytes (the swizzle selection logic in mla_sm120.cu) to explicitly handle supported values (e.g., 128 -> CU_TENSOR_MAP_SWIZZLE_128B, 64 -> CU_TENSOR_MAP_SWIZZLE_64B) and add a fallback error path (log and return/throw) for any other partBytes, mirroring the runtime-check-and-fail pattern used in makeTensorMapForPagedKVCache in tensorMap.cpp so misconfigurations are caught at runtime.
1868-1879: Consider deduplicating SMEM configuration code.The
configureKernel()function duplicates the SMEM validation logic from the static lambda inlaunchMLA(lines 1763-1779). Both perform identical checks andcudaFuncSetAttributecalls.Optional: Extract shared SMEM configuration
// Extract to a shared helper to avoid duplication: static uint32_t configureMhaSmem() { uint32_t size; checkCuda(cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize))); int devMaxShmem = 0; checkCuda(cudaDeviceGetAttribute(&devMaxShmem, cudaDevAttrMaxSharedMemoryPerBlockOptin, 0)); if (size > (uint32_t)devMaxShmem) { throw std::runtime_error("XQA MLA kernel requires " + std::to_string(size) + " bytes shared memory per block, but " "device opt-in max is " + std::to_string(devMaxShmem) + ". BF16 MLA needs 128 KB (e.g. SM12x)."); } checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributePreferredSharedMemoryCarveout, cudaSharedmemCarveoutMaxShared)); checkCuda(cudaFuncSetAttribute(kernel_mha, cudaFuncAttributeMaxDynamicSharedMemorySize, size)); return size; }🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` around lines 1868 - 1879, The SMEM validation and cudaFuncSetAttribute logic is duplicated between configureKernel() and the static lambda in launchMLA; extract that shared logic into a single helper (e.g., configureMhaSmem) that reads smemSize via cudaMemcpyFromSymbol, queries cudaDevAttrMaxSharedMemoryPerBlockOptin, throws the same runtime_error when size exceeds devMaxShmem, and calls cudaFuncSetAttribute on kernel_mha for cudaFuncAttributePreferredSharedMemoryCarveout and cudaFuncAttributeMaxDynamicSharedMemorySize, then call this helper from both configureKernel() and the launchMLA lambda to remove duplication.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Inline comments:
In `@flashinfer/mla.py`:
- Around line 604-609: The boolean assignments for fp8_ok and bf16_ok are split
across parens and triggered ruff-format; change each to a single-line boolean
expression (e.g., set fp8_ok to "query.dtype == torch.float8_e4m3fn and
kv_cache.dtype == torch.float8_e4m3fn" and bf16_ok to "query.dtype ==
torch.bfloat16 and kv_cache.dtype == torch.bfloat16") so formatting matches ruff
expectations, then run pre-commit (pre-commit run --all-files) to ensure the
repo is formatted; locate these edits at the fp8_ok and bf16_ok assignments in
flashinfer/mla.py.
---
Nitpick comments:
In `@csrc/xqa/mla_sm120.cu`:
- Around line 1733-1734: The swizzle selection should not silently fall back to
64B for unexpected partBytes; update the code around
partBytes/partElems/elemBytes (the swizzle selection logic in mla_sm120.cu) to
explicitly handle supported values (e.g., 128 -> CU_TENSOR_MAP_SWIZZLE_128B, 64
-> CU_TENSOR_MAP_SWIZZLE_64B) and add a fallback error path (log and
return/throw) for any other partBytes, mirroring the runtime-check-and-fail
pattern used in makeTensorMapForPagedKVCache in tensorMap.cpp so
misconfigurations are caught at runtime.
- Around line 1868-1879: The SMEM validation and cudaFuncSetAttribute logic is
duplicated between configureKernel() and the static lambda in launchMLA; extract
that shared logic into a single helper (e.g., configureMhaSmem) that reads
smemSize via cudaMemcpyFromSymbol, queries
cudaDevAttrMaxSharedMemoryPerBlockOptin, throws the same runtime_error when size
exceeds devMaxShmem, and calls cudaFuncSetAttribute on kernel_mha for
cudaFuncAttributePreferredSharedMemoryCarveout and
cudaFuncAttributeMaxDynamicSharedMemorySize, then call this helper from both
configureKernel() and the launchMLA lambda to remove duplication.
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csrc/xqa/defines.hcsrc/xqa/mla_sm120.cucsrc/xqa/tensorMap.cppflashinfer/jit/xqa.pyflashinfer/mla.py
… fix ruff format - Simplify partElemsK to direct assignment (always 64 for both FP8 and BF16) - Simplify tokensPerTile ternary: is_fp8 ? 64 : 32 (remove unreachable branch) - Simplify nbKBufs ternary: is_fp8 ? 12 : 2 (remove unreachable branch) - Deduplicate shared memory configuration: launchMLA now calls configureKernel() instead of duplicating the smem validation + attribute setup logic - Fix ruff format: collapse bf16_ok multi-line expression to single line in mla.py Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Actionable comments posted: 1
🧹 Nitpick comments (1)
csrc/xqa/mla_sm120.cu (1)
1765-1765: Consider consolidating duplicate static initialization.There are two static initializations calling
configureKernel(): one local tolaunchMLA(line 1765) and one at file scope (line 1869). Both configure the same kernel attributes. While this isn't incorrect, it's slightly wasteful. The local static inlaunchMLAcould be removed sincelaunchMLAFlashInferalready relies on the file-scope initialization, andlaunchMLAcould use the same approach.However, if this pattern matches the existing codebase structure, it's acceptable to keep for consistency.
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` at line 1765, Duplicate static initialization: remove the local static uint32_t const hostSmemSize = configureKernel() in launchMLA and have launchMLA use the existing file-scope initialization that launchMLAFlashInfer relies on; specifically, delete the local hostSmemSize declaration in launchMLA and reference the file-scope hostSmemSize (configured by configureKernel()) instead to avoid calling configureKernel() twice.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Inline comments:
In `@flashinfer/mla.py`:
- Around line 772-779: The public function xqa_batch_decode_with_kv_cache_mla
currently only validates dtypes but lacks the GPU compute-capability guard
present in trtllm_batch_decode_with_kv_cache_mla; add the same SM120/SM121
compute-capability check at the start of xqa_batch_decode_with_kv_cache_mla
(before the dtype checks) and raise a clear RuntimeError (or ValueError
consistent with the other check) when the device does not meet the required
SM120/SM121 capability so direct calls produce an explicit error instead of
kernel failures.
---
Nitpick comments:
In `@csrc/xqa/mla_sm120.cu`:
- Line 1765: Duplicate static initialization: remove the local static uint32_t
const hostSmemSize = configureKernel() in launchMLA and have launchMLA use the
existing file-scope initialization that launchMLAFlashInfer relies on;
specifically, delete the local hostSmemSize declaration in launchMLA and
reference the file-scope hostSmemSize (configured by configureKernel()) instead
to avoid calling configureKernel() twice.
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…zle assert - Add compute capability check to xqa_batch_decode_with_kv_cache_mla() to match the existing guard in batch_decode_with_kv_cache_mla() - Remove duplicate static configureKernel() call inside launchMLA; the file-scope static init at line 1869 is sufficient for both launchMLA and launchMLAFlashInfer - Add assert(partBytes == 128 || partBytes == 64) before swizzle selection to catch unexpected values early Contributed by Second Nature Computing (https://joinsecondnature.com) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Actionable comments posted: 3
🧹 Nitpick comments (1)
csrc/xqa/mla_sm120.cu (1)
703-705: Remove duplicateloaderK.load()in regQ prefetch loop.The same
loaderK.load(idxAtomBx2)is written twice toregKBuf[idxInstKPrefetch][idxAtomBx2]in one iteration. Keeping one load reduces unnecessary SMEM traffic.Suggested fix
- regKBuf[idxInstKPrefetch][idxAtomBx2] = loaderK.load(idxAtomBx2); if (shouldTestWait(idxInstKPrefetch, idxAtomBx2) && prefetch) { kBarWaiterNext.testWait(); } @@ if (prefetch) { regKBuf[idxInstKPrefetch][idxAtomBx2] = loaderK.load(idxAtomBx2); }Also applies to: 717-719
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` around lines 703 - 705, The prefetch loop currently calls loaderK.load(idxAtomBx2) twice and writes it twice into regKBuf (using AtomBx2 const& atomBx2, regKBuf[idxInstKPrefetch][idxAtomBx2] = loaderK.load(idxAtomBx2)); fix by performing a single load into a temporary (or directly assign once) and reuse that value for any needed writes/uses; update the regQ prefetch loop where loaderK.load is duplicated (the block referencing idxInstKPrefetch, idxAtomBx2, shouldTestWait and prefetch) and apply the same single-load change to the similar occurrence around the 717-719 region.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Inline comments:
In `@csrc/xqa/mla_sm120.cu`:
- Around line 1855-1861: The code currently queries device 0 when checking
shared-memory capability; update configureKernel() to first obtain the active
CUDA device (e.g., call cudaGetDevice to get an int currentDev) and then pass
that device ordinal into cudaDeviceGetAttribute instead of the hardcoded 0;
adjust the devMaxShmem check/throw path to use this queried device and keep
error handling as-is so the validation reflects the actual device where kernels
will run (references: configureKernel(), devMaxShmem, cudaDeviceGetAttribute).
In `@flashinfer/mla.py`:
- Around line 602-603: Replace the inline compute-capability checks (the if
using get_compute_capability(query.device)[0] != 12) on the public APIs in
flashinfer/mla.py with the `@backend_requirement` decorator: add/attach
`@backend_requirement` to those API functions and implement/provide the required
helper methods is_compute_capability_supported(cc) and is_backend_supported() on
the backend so the decorator can enforce the SM120/SM121 constraint; do the same
refactor for the second API guarded at lines 772-774. Ensure the decorator
expresses the SM120/SM121 requirement instead of raising ValueError inline.
- Around line 602-603: The check in mla.py uses
get_compute_capability(query.device)[0] != 12 which only tests the major
version; replace that guard with a call to is_sm12x_supported(query.device) (or
the existing SM12x utility) in the XQA MLA entry point(s) so the code calls
is_sm12x_supported(...) instead of comparing the major version, and update both
the current location (the block referencing get_compute_capability) and the
other occurrence around lines 772-774 to use is_sm12x_supported for consistent,
accurate SM12x/CUDA compatibility checking.
---
Nitpick comments:
In `@csrc/xqa/mla_sm120.cu`:
- Around line 703-705: The prefetch loop currently calls
loaderK.load(idxAtomBx2) twice and writes it twice into regKBuf (using AtomBx2
const& atomBx2, regKBuf[idxInstKPrefetch][idxAtomBx2] =
loaderK.load(idxAtomBx2)); fix by performing a single load into a temporary (or
directly assign once) and reuse that value for any needed writes/uses; update
the regQ prefetch loop where loaderK.load is duplicated (the block referencing
idxInstKPrefetch, idxAtomBx2, shouldTestWait and prefetch) and apply the same
single-load change to the similar occurrence around the 717-719 region.
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| if get_compute_capability(query.device)[0] != 12: | ||
| raise ValueError("XQA MLA is only supported on SM120/SM121 GPUs") |
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🛠️ Refactor suggestion | 🟠 Major
Prefer @backend_requirement for these capability-gated public APIs.
Both APIs now have explicit architecture requirements, so the requirement should be declared via the backend decorator contract instead of only inline checks.
As per coding guidelines Use @backend_requirement decorator on APIs that have compute capability requirements and provide is_compute_capability_supported(cc) and is_backend_supported() methods.
Also applies to: 772-774
🧰 Tools
🪛 Ruff (0.15.2)
[warning] 603-603: Avoid specifying long messages outside the exception class
(TRY003)
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.
In `@flashinfer/mla.py` around lines 602 - 603, Replace the inline
compute-capability checks (the if using get_compute_capability(query.device)[0]
!= 12) on the public APIs in flashinfer/mla.py with the `@backend_requirement`
decorator: add/attach `@backend_requirement` to those API functions and
implement/provide the required helper methods
is_compute_capability_supported(cc) and is_backend_supported() on the backend so
the decorator can enforce the SM120/SM121 constraint; do the same refactor for
the second API guarded at lines 772-774. Ensure the decorator expresses the
SM120/SM121 requirement instead of raising ValueError inline.
Use is_sm12x_supported() instead of major-only checks.
The current guard only checks major == 12, which can admit unsupported SM12x/CUDA combinations. Please use the SM12x utility check consistently in both entry points.
Suggested fix
from .utils import (
MaskMode,
check_shape_dtype_device,
determine_mla_backend,
device_support_pdl,
get_compute_capability,
get_device_sm_count,
+ is_sm12x_supported,
log2e,
)
@@
- if get_compute_capability(query.device)[0] != 12:
+ if not is_sm12x_supported(query.device):
raise ValueError("XQA MLA is only supported on SM120/SM121 GPUs")
@@
- cc = get_compute_capability(query.device)
- if cc[0] != 12:
- raise ValueError("XQA MLA BF16 is only supported on SM120/SM121 GPUs")
+ if not is_sm12x_supported(query.device):
+ raise ValueError("XQA MLA is only supported on SM120/SM121 GPUs")Also applies to: 772-774
🧰 Tools
🪛 Ruff (0.15.2)
[warning] 603-603: Avoid specifying long messages outside the exception class
(TRY003)
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.
In `@flashinfer/mla.py` around lines 602 - 603, The check in mla.py uses
get_compute_capability(query.device)[0] != 12 which only tests the major
version; replace that guard with a call to is_sm12x_supported(query.device) (or
the existing SM12x utility) in the XQA MLA entry point(s) so the code calls
is_sm12x_supported(...) instead of comparing the major version, and update both
the current location (the block referencing get_compute_capability) and the
other occurrence around lines 772-774 to use is_sm12x_supported for consistent,
accurate SM12x/CUDA compatibility checking.
configureKernel() was always querying device 0 for max shared memory, which would fail on multi-GPU systems where the active device differs. Use cudaGetDevice() to query the actual current device. Contributed by Second Nature Computing (https://joinsecondnature.com) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Replace manual get_compute_capability()[0] != 12 checks with the is_sm12x_supported() utility which also validates the CUDA toolkit version (SM120a needs CUDA 12.8, SM121a needs CUDA 13.0). Contributed by Second Nature Computing (https://joinsecondnature.com) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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🧹 Nitpick comments (2)
csrc/xqa/mla_sm120.cu (2)
1717-1719: Verify the conditional limit values.Both branches of the conditional evaluate to the same value:
is_bf16 ? 101376 : 99 * 1024→101376or101376(since 99 × 1024 = 101376)If this is intentional (both precisions have the same limit), the conditional can be simplified to just
101376. If BF16 was meant to have a different limit, please verify the intended values.Simplification if both limits are intentionally the same
-static constexpr uint32_t kSmemLimitBytes = is_bf16 ? 101376 : 99 * 1024; +static constexpr uint32_t kSmemLimitBytes = 101376; // 99KB opt-in limit🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` around lines 1717 - 1719, The ternary used for kSmemLimitBytes is redundant because is_bf16 ? 101376 : 99 * 1024 yields the same numeric value; either simplify kSmemLimitBytes to the single literal 101376 (remove the conditional) or, if BF16 was meant to have a different limit, correct the BF16 branch to the intended value (e.g., change the first operand of the ternary) and keep the conditional; ensure the static_assert(smemSize <= kSmemLimitBytes, ...) remains using the updated kSmemLimitBytes and that any references to is_bf16/kSmemLimitBytes reflect the chosen fix.
1267-1268: Intentional unroll suppression or typo?
#pragma unroll 1explicitly prevents unrolling, which is unusual inside a performance-critical inner loop. Typically this would be#pragma unroll(full unroll) or omitted entirely.If this is intentional to reduce register pressure for BF16, please add a brief comment. Otherwise, consider changing to
#pragma unrollfor consistency with the FP8 path.🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@csrc/xqa/mla_sm120.cu` around lines 1267 - 1268, The loop with "for (uint32_t idxGrain = 0; idxGrain < grainsPerVPart; idxGrain++)" is annotated with "#pragma unroll 1" which explicitly disables unrolling and differs from the FP8 path; either remove or change it to "#pragma unroll" to allow full unrolling for performance consistency, or if the suppression is intentional to reduce register pressure for BF16, add a one-line comment above the pragma explaining that rationale (mentioning BF16 register pressure and why unrolling would be detrimental) so future readers know this is deliberate; update the BF16-related kernel/loop containing idxGrain/grainsPerVPart to follow one of these two options.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Nitpick comments:
In `@csrc/xqa/mla_sm120.cu`:
- Around line 1717-1719: The ternary used for kSmemLimitBytes is redundant
because is_bf16 ? 101376 : 99 * 1024 yields the same numeric value; either
simplify kSmemLimitBytes to the single literal 101376 (remove the conditional)
or, if BF16 was meant to have a different limit, correct the BF16 branch to the
intended value (e.g., change the first operand of the ternary) and keep the
conditional; ensure the static_assert(smemSize <= kSmemLimitBytes, ...) remains
using the updated kSmemLimitBytes and that any references to
is_bf16/kSmemLimitBytes reflect the chosen fix.
- Around line 1267-1268: The loop with "for (uint32_t idxGrain = 0; idxGrain <
grainsPerVPart; idxGrain++)" is annotated with "#pragma unroll 1" which
explicitly disables unrolling and differs from the FP8 path; either remove or
change it to "#pragma unroll" to allow full unrolling for performance
consistency, or if the suppression is intentional to reduce register pressure
for BF16, add a one-line comment above the pragma explaining that rationale
(mentioning BF16 register pressure and why unrolling would be detrimental) so
future readers know this is deliberate; update the BF16-related kernel/loop
containing idxGrain/grainsPerVPart to follow one of these two options.
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Actionable comments posted: 1
♻️ Duplicate comments (1)
flashinfer/mla.py (1)
603-604: 🛠️ Refactor suggestion | 🟠 MajorUse
@backend_requirementfor these capability-gated public APIs.Both entry points are public APIs and have explicit compute-capability requirements, so this should be enforced through the backend requirement contract rather than inline checks.
As per coding guidelines
Use@backend_requirementdecorator on APIs that have compute capability requirements and provide is_compute_capability_supported(cc) and is_backend_supported() methods.Also applies to: 773-774
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed. In `@flashinfer/mla.py` around lines 603 - 604, Replace the inline compute-capability checks (e.g., the is_sm12x_supported(query.device) conditional) with the standard backend requirement decorator: add `@backend_requirement` and implement/attach is_compute_capability_supported(cc) and is_backend_supported() for the MLA backend so the public entry points are guarded by the backend contract rather than raising ValueError inline; remove the inline checks in the same function (and the other occurrence at the 773-774 check) and ensure the decorator references the same compute capability predicate formerly done by is_sm12x_supported.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.
Inline comments:
In `@flashinfer/mla.py`:
- Around line 603-604: The ValueError raised when checking is_sm12x_supported()
is misleading because that helper also enforces a minimum CUDA toolkit version;
update both occurrences (the conditional using is_sm12x_supported in mla.py) to
include the CUDA toolkit minimum in the rejection message (e.g., "requires SM12x
GPU and CUDA toolkit >= <min_version>") — obtain the actual minimum either from
the is_sm12x_supported-related helper or hardcode the documented minimum so the
error communicates both GPU SM and CUDA-version requirements.
---
Duplicate comments:
In `@flashinfer/mla.py`:
- Around line 603-604: Replace the inline compute-capability checks (e.g., the
is_sm12x_supported(query.device) conditional) with the standard backend
requirement decorator: add `@backend_requirement` and implement/attach
is_compute_capability_supported(cc) and is_backend_supported() for the MLA
backend so the public entry points are guarded by the backend contract rather
than raising ValueError inline; remove the inline checks in the same function
(and the other occurrence at the 773-774 check) and ensure the decorator
references the same compute capability predicate formerly done by
is_sm12x_supported.
|
/bot run |
is_sm12x_supported() also checks CUDA toolkit version, so the error message should mention the actual requirements: SM120a needs CUDA 12.8+, SM121a needs CUDA 13.0+. Contributed by Second Nature Computing (https://joinsecondnature.com) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
|
[SUCCESS] Pipeline #45437396: 10/20 passed |
saltyminty
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saltyminty
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Do we need any test coverage for BF16 MLA? The existing XQA tests only cover fp8.
| cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize)); | ||
| cudaFuncSetAttribute(kernel_mha, cudaFuncAttributeMaxDynamicSharedMemorySize, size); | ||
| checkCuda(cudaMemcpyFromSymbol(&size, smemSize, sizeof(smemSize))); | ||
| int dev = 0; |
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Is this intended to be hardcoded to device 0?
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No — it's initialized to 0 then immediately overwritten by cudaGetDevice(&dev) on the next line. Just a default before the query.
|
@saltyminty Good point on BF16 MLA test coverage. The existing XQA tests in This PR doesn't add a BF16 MLA path; it fixes 10 bugs in the existing FP8 MLA SM120 kernel (warp shuffle masks, accumulator indexing, shared memory layout, etc.). So FP8 test coverage is the right scope here. BF16 MLA on SM120 would be a separate feature/PR. |
Previous run had simultaneous AOT build failures across multiple architectures (arm64/cu126, x64/cu128-130, etc.) and JIT cancellations — consistent with spot instance preemption. All JIT reruns passed. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
blake-snc
requested review from
aleozlx,
samuellees,
sricketts,
yongwww and
yyihuang
as code owners
6 participants
Summary
Fixes 10 bugs in PR #2675 (BF16 XQA MLA on SM120) that cause the kernel to produce 100% NaN output. Validated on SM121a (DGX Spark GB10) — all configurations now produce correct results with max_diff < 11 microunits vs PyTorch reference.
This PR builds on #2675's foundation and adds the fixes needed to make BF16 XQA MLA actually work on SM120/SM121 hardware.
Bugs fixed
gen_xqa_module_mla()blocked BF16 compilationpartElemsVto 64 for BF16.b8ldmatrix transpose scrambles BF16 — replaced with.b16transposestoreOrderedXToShmBf16OOB WarpAcc indexing — rewrote with correct MMA register mappingidxAtomBx2==2never triggers for BF16 —tileNbAtomBx2=2means range 0..1, condition never fires → uninitialized Q registers → garbage GEMM0 → NaN. Fixed withconstexpr qPrefetchAtomBx2 = min(2, tileNbAtomBx2-1)Files changed
csrc/xqa/defines.h— Add BF16 MLA preprocessor pathcsrc/xqa/mla_sm120.cu— All 10 kernel fixescsrc/xqa/tensorMap.cpp— Better error messages for unsupported swizzle sizesflashinfer/jit/xqa.py— Accept BF16 dtype, pass-DMLA_BF16=1flagValidation on SM121a (DGX Spark)
Correctness vs PyTorch reference (Q×K^T softmax, then ×V):
Related Issues
Test plan
Contributed by Second Nature Computing (https://joinsecondnature.com)
🤖 Generated with Claude Code
Summary by CodeRabbit
New Features
Improvements
Behavioral
Bug Fixes