Xtensa patches (16.x) (Do not merge, PR created for easier review only) #82

gerekon · 2023-09-01T10:45:46Z

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Initial codegen support for simple ALU operations.

Constant Pool.

operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

constructs.

Also lower SHL, SRA, SRL with register operands.

patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

Add support for llvm.{frameaddress,returnaddress} intrinsics.

Implement volatile load/store from/to volatile memory location.

scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.

Also implement User Registers class.

SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands.

operations.

Extend Xtensa C ABI test to include v1i1 parameters.

Adding __builtin_xtensa_movt_s and __builtin_xtensa_movf_s intrinsics. Adding intrincic patterns to MOVT_S anf MOVF_S definitions.

This patch adds a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms.

Some Xtensa targets may still use GAS as a default assemblwr through -fno-integrated-as option. These changes make the assembly output compatible with GAS by default. - GAS does not recognize .word but .2byte works for both - Dwarf CFI is not supported by GAS. Option -fdwarf-exceptions can still turn it on but there is no option to turn it off, so an opt-in approach is more portable.

Xtensa architecture uses v2i1 (BR2 reg class) and v4i1 (BR4 reg class) boolean vectors as arguments for HIFI instructions: - vector compare, e.g.: AE_EQ16X4 - vector conditional move, e.g: AE_MOVT16X4

This option is passed to GNU AS and makes Xtensa compiler driver compatible with GCC.

Intrinsics: __builtin_xtensa_ae_int32x2 and builtin_xtensa_int32 are convenience functions for easy integer-vector and vector-vector conversions that conform to Xtensa coding style. Xtensa C dialect allows for implicit conversion between wider and narrower vector (via shuffle) and between integer and any vector (via broadcast). Standard Clang vectors do not support this, so these functions provide a handicap for better portability.

andreisfr added 30 commits June 1, 2023 00:42

[Xtensa] Initial support of the ALU operations.

5642dcc

Initial codegen support for simple ALU operations.

[Xtensa] Codegen support for memory operations

8f68354

[Xtensa] Add Constant Pool

3ae2a4f

[Xtensa] Implement assembler representation of the

dbf40cc

Constant Pool.

[Xtensa] Implement lowering constants.

2bbf896

[Xtensa] Add support of the Xtensa function calls

bcc6887

[Xtensa] Implement lowering ConstantPool and address

4ba0aed

operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

[Xtensa] Implement emitPrologue/emitEpilogue

d71d2cb

[Xtensa] Lower stack operations

3050c28

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

[Xtensa] Implement lowering SELECT_CC, SETCC

68a74e0

[Xtensa] Support for a variety of additional LLVM IR

54d7584

constructs.

[Xtensa] Lower SHIFT PARTS and shift operations.

5ea853c

Also lower SHL, SRA, SRL with register operands.

[Xtensa] Implement load pseudo operations and

f5758e5

patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

[Xtensa] Support for variable arguments

6d26048

[Xtensa] Implement lowering BR_JT operation

be1bdef

[Xtensa] Support for address intrinsics.

25bded7

Add support for llvm.{frameaddress,returnaddress} intrinsics.

[Xtensa] Add basic support for inline asm constraints

261c7c3

[Xtensa] Implement volatile load/store.

58dd919

Implement volatile load/store from/to volatile memory location.

[Xtensa] Implement branch analysis

42b0dab

[Xtensa] Implement support for the BranchRelaxation

3eb202b

[Xtensa] Implement code density feature operations

dc4791c

[Xtensa] Add code size reduction pass.

8dde053

[Xtensa] Implement Windowed feature operations

f16d299

[Xtensa] Implement Windowed Call ABI

2d9519d

[Xtensa] Reserve an emergency spill slot for

83e7590

scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.

[Xtensa] Implement Boolean feature operations

7d66c45

[Xtensa] Implement Floating-Point feature operations.

536cd71

Also implement User Registers class.

[Xtensa] Lowering Floating-Point Operations

f39e50b

SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands.

[Xtensa] Implement DAG Combine for FADD and FSUB

f9bad2d

operations.

[Xtensa] Implement Loop, SEXT and NSA features.

8125470

maciej-czekaj added 29 commits December 12, 2023 12:58

[Xtensa] Add ABI test for xtbool

0f9a7e0

Extend Xtensa C ABI test to include v1i1 parameters.

[Xtensa] Implement conditional move instrinsics

c10c1d0

Adding __builtin_xtensa_movt_s and __builtin_xtensa_movf_s intrinsics. Adding intrincic patterns to MOVT_S anf MOVF_S definitions.

[Xtensa] Add basic float intrinsics

fa452c5

[Xtensa] Implement remaining floating point intrinsics

ffbc43a

[Xtensa] Add Cannonlake CPU

4e3ffb9

This patch adds a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms.

[Xtensa] Add HIFI3 intrinsic functions

3fd4287

[Xtensa] Add HIFI3 register classes

642ee96

[Xtensa] Add HIFI3 target feature

c882b94

[Xtensa] Add HIFI3 instructions

ae6cc7a

[Xtensa] Add support for boolean vectors

ef9b67e

Xtensa architecture uses v2i1 (BR2 reg class) and v4i1 (BR4 reg class) boolean vectors as arguments for HIFI instructions: - vector compare, e.g.: AE_EQ16X4 - vector conditional move, e.g: AE_MOVT16X4

[Xtensa] Add HIFI3 instruction lowering

d2a8048

[Xtensa] Fix alignment in LowerVACOPY()

db19868

[Xtensa] Add HIFI3 instruction selection patterns

adfea59

[Xtensa] Add codegen tests for vector operators

f052ac6

[Xtensa] Add codegen support for HIFI3 intrinsics

f33e92e

[Xtensa] Support bit vectors in BRegFixupPass

25f7e5a

[Xtensa] Add codegen tests for bit vectors

bc170f6

[Xtensa] Remove unsspported intrinsic xt_conjc_s

26ce436

[Xtensa] Add HIFI3 intrinsic definitions to clang

08208d7

[Xtensa] Add constant checks for HIFI3 intrinsics

2870952

[Xtensa] Support HIFI3 vectors in LLVM calls

3e67039

[Xtensa] Add HIFI3 intrinsics to Clang codegen

2157441

[Xtensa] Fix xt_lsxp builtin definition

3d0f4f5

[Xtensa] Support bool vectors in LLVM calls

913dc40

[Xtensa] Add --text-section-literals option

7113592

This option is passed to GNU AS and makes Xtensa compiler driver compatible with GCC.

[Xtensa] Add HIFI3 C types and intrinsics

2849b71

[Xtensa] Add support for decoding from HIFI namespace

f258e0a

gerekon closed this Dec 28, 2023

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Xtensa patches (16.x) (Do not merge, PR created for easier review only) #82

Xtensa patches (16.x) (Do not merge, PR created for easier review only) #82

gerekon commented Sep 1, 2023

Xtensa patches (16.x) (Do not merge, PR created for easier review only) #82

Xtensa patches (16.x) (Do not merge, PR created for easier review only) #82

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gerekon commented Sep 1, 2023