[Xtensa] Add CLAMPS feature

espressif · Aug 28, 2023 · c81a5b8 · c81a5b8
1 parent 26ca9b6
commit c81a5b8
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Showing 14 changed files with 87 additions and 23 deletions.
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -381,7 +381,7 @@ struct XtensaOperand : public MCParsedAsmOperand {
     return false;
   }
 
-  bool isseimm7_22() const { return isImm(7, 22); }
+  bool isimm7_22() const { return isImm(7, 22); }
 
   bool isSelect_2() const { return isImm(0, 1); }
 
@@ -741,7 +741,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_Invalidentry_imm12:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected immediate in range [0, 32760]");
-  case Match_Invalidseimm7_22:
+  case Match_Invalidimm7_22:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected immediate in range [7, 22]");
   case Match_InvalidSelect_2:

diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -576,9 +576,9 @@ static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm,
-                                           int64_t Address,
-                                           const void *Decoder) {
+static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm,
+                                         int64_t Address,
+                                         const void *Decoder) {
   assert(isUInt<4>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(Imm + 7));
   return MCDisassembler::Success;

diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -438,8 +438,8 @@ void XtensaInstPrinter::printB4constu_AsmOperand(const MCInst *MI, int OpNum,
     printOperand(MI, OpNum, O);
 }
 
-void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum,
-                                                  raw_ostream &O) {
+void XtensaInstPrinter::printImm7_22_AsmOperand(const MCInst *MI, int OpNum,
+                                                raw_ostream &O) {
   if (MI->getOperand(OpNum).isImm()) {
     int64_t Value = MI->getOperand(OpNum).getImm();
     assert((Value >= 7 && Value <= 22) &&

diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
@@ -69,7 +69,7 @@ class XtensaInstPrinter : public MCInstPrinter {
   void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
-  void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+  void printImm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);

diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -139,9 +139,9 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
-  uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
-                               SmallVectorImpl<MCFixup> &Fixups,
-                               const MCSubtargetInfo &STI) const;
+  uint32_t getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
 
   uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
@@ -628,9 +628,9 @@ XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,
 }
 
 uint32_t
-XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
-                                         SmallVectorImpl<MCFixup> &Fixups,
-                                         const MCSubtargetInfo &STI) const {
+XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   uint32_t res = static_cast<uint32_t>(MO.getImm());
 

diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -47,6 +47,11 @@ def FeatureSEXT             : SubtargetFeature<"sext", "HasSEXT", "true",
 def HasSEXT                 : Predicate<"Subtarget->hasSEXT()">,
                                          AssemblerPredicate<(all_of FeatureSEXT)>;
 
+def FeatureCLAMPS           : SubtargetFeature<"clamps", "HasCLAMPS", "true",
+                                               "Enable Xtensa CLAMPS option">;
+def HasCLAMPS               : Predicate<"Subtarget->hasCLAMPS()">,
+                                         AssemblerPredicate<(all_of FeatureCLAMPS)>;
+
 def FeatureNSA              : SubtargetFeature<"nsa", "HasNSA", "true",
                                                "Enable Xtensa NSA option">;
 def HasNSA                  : Predicate<"Subtarget->hasNSA()">,
@@ -185,21 +190,21 @@ def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC
                      FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
                      FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor,
                      FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
-                     FeatureMINMAX]>;
+                     FeatureMINMAX, FeatureCLAMPS]>;
 
 def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException,
                        FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>;
 
 def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA,  FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR,
                        FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt,
                        FeatureRelocatableVector,	FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX,
-                       FeatureESP32S2Ops]>;
+                       FeatureCLAMPS, FeatureESP32S2Ops]>;
 
 def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT,
                        FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
                        FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor,
                        FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
-                       FeatureMINMAX, FeatureESP32S3Ops]>;
+                       FeatureMINMAX, FeatureCLAMPS, FeatureESP32S3Ops]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1334,13 +1334,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size =
 // SEXT Instructions
 //===----------------------------------------------------------------------===//
 
-def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, seimm7_22:$imm),
+def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
                    "sext\t$r, $s, $imm", []>, Requires<[HasSEXT]> {
   bits<4> imm;
 
   let t = imm;
 }
 
+//===----------------------------------------------------------------------===//
+// CLAMPS Instructions
+//===----------------------------------------------------------------------===//
+
+def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
+                   "clamps\t$r, $s, $imm", []>, Requires<[HasSEXT]> {
+  bits<4> imm;
+
+  let t = imm;
+}
+
 //===----------------------------------------------------------------------===//
 // NSA Instructions
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td
@@ -168,11 +168,11 @@ def b4constu: Immediate<i32,
   let DecoderMethod = "decodeB4constuOperand";
 }
 
-// seimm7_22 predicate - Immediate in the range [7,22] for sign extend
-def Seimm7_22_AsmOperand: ImmAsmOperand<"seimm7_22">;
-def seimm7_22: Immediate<i32, [{ return Imm >= 7 && Imm <= 22; }], "Seimm7_22_AsmOperand"> {
-  let EncoderMethod = "getSeimm7_22OpValue";
-  let DecoderMethod = "decodeSeimm7_22Operand";
+// imm7_22 predicate - Immediate in the range [7,22] for sign extend and clamps
+def Imm7_22_AsmOperand: ImmAsmOperand<"imm7_22">;
+def imm7_22: Immediate<i32, [{ return Imm >= 7 && Imm <= 22; }], "Imm7_22_AsmOperand"> {
+  let EncoderMethod = "getImm7_22OpValue";
+  let DecoderMethod = "decodeImm7_22Operand";
 }
 
 // select_256 predicate - Immediate in the range [0,255]

diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -51,6 +51,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasBoolean = false;
   HasLoop = false;
   HasSEXT = false;
+  HasCLAMPS = false;
   HasNSA = false;
   HasMINMAX = false;
   HasMul16 = false;

diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -56,6 +56,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   // Enable Xtensa Sign Extend option
   bool HasSEXT;
 
+  // Enable Xtensa CLAMPS option
+  bool HasCLAMPS;
+
   // Enable Xtensa NSA option
   bool HasNSA;
 
@@ -160,6 +163,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
 
   bool hasSEXT() const { return HasSEXT; }
 
+  bool hasCLAMPS() const { return HasCLAMPS; }
+
   bool hasNSA() const { return HasNSA; }
 
   bool hasMINMAX() const { return HasMINMAX; }

diff --git a/llvm/test/MC/Xtensa/xtensa-clamps-invalid.s b/llvm/test/MC/Xtensa/xtensa-clamps-invalid.s
@@ -0,0 +1,9 @@
+# RUN: not llvm-mc %s -triple=xtensa -mattr=+clamps 2>&1 | FileCheck %s
+
+# imm7_22
+clamps a3, a2, 6
+# CHECK: :[[#@LINE-1]]:16: error: expected immediate in range [7, 22]
+
+# imm7_22
+clamps a3, a2, 23
+# CHECK: :[[#@LINE-1]]:16: error: expected immediate in range [7, 22]
diff --git a/llvm/test/MC/Xtensa/xtensa-clamps-valid.s b/llvm/test/MC/Xtensa/xtensa-clamps-valid.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+clamps -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+# Instruction format RRR
+# CHECK-INST: clamps a3, a2, 7
+# CHECK: encoding: [0x00,0x32,0x33]
+clamps a3, a2, 7
+
+# Instruction format RRR
+# CHECK-INST: clamps a3, a2, 22
+# CHECK: encoding: [0xf0,0x32,0x33]
+clamps a3, a2, 22
diff --git a/llvm/test/MC/Xtensa/xtensa-sext-invalid.s b/llvm/test/MC/Xtensa/xtensa-sext-invalid.s
@@ -0,0 +1,9 @@
+# RUN: not llvm-mc %s -triple=xtensa -mattr=+sext 2>&1 | FileCheck %s
+
+# imm7_22
+sext a3, a2, 6
+# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [7, 22]
+
+# imm7_22
+sext a3, a2, 23
+# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [7, 22]
diff --git a/llvm/test/MC/Xtensa/xtensa-sext-valid.s b/llvm/test/MC/Xtensa/xtensa-sext-valid.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=xtensa -mattr=+sext -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+# Instruction format RRR
+# CHECK-INST: sext a3, a2, 7
+# CHECK: encoding: [0x00,0x32,0x23]
+sext a3, a2, 7
+
+# Instruction format RRR
+# CHECK-INST: sext a3, a2, 22
+# CHECK: encoding: [0xf0,0x32,0x23]
+sext a3, a2, 22