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Xtensa] Use B0 register for FP cmp operations.
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The virtual bool registers allocation from BR class may cause
situation when we need to spill such 1-bit registers, this would cause
performance degradation due to load/store operations of the 32-bit BR register.
The performance improvement from using virtual bool registers is not
significant. So, just use only B0 register for FP compare operations.
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andreisfr committed Apr 14, 2022
1 parent ce86f67 commit 7507e37
Showing 1 changed file with 9 additions and 10 deletions.
19 changes: 9 additions & 10 deletions llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2052,15 +2052,15 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
(MI.getOpcode() == Xtensa::SELECT_CC_FP_INT)) {
int BrKind = 0;
int CmpKind = 0;
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
unsigned b = RegInfo.createVirtualRegister(RC);
unsigned b = Xtensa::B0;

GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
BuildMI(BB, DL, TII.get(CmpKind), b)
.addReg(LHS.getReg())
.addReg(RHS.getReg());
BuildMI(BB, DL, TII.get(BrKind)).addReg(b).addMBB(sinkMBB);
BuildMI(BB, DL, TII.get(BrKind))
.addReg(b, RegState::Kill)
.addMBB(sinkMBB);
} else {
bool BrInv = false;
int BrKind = GetBranchKind(Cond.getImm(), BrInv);
Expand Down Expand Up @@ -3115,16 +3115,15 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
MachineBasicBlock *TargetBB = MI.getOperand(3).getMBB();
int BrKind = 0;
int CmpKind = 0;
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
unsigned RegB = Xtensa::B0;

unsigned RegB = RegInfo.createVirtualRegister(RC);
GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
BuildMI(*MBB, MI, DL, TII.get(CmpKind), RegB)
.addReg(LHS.getReg())
.addReg(RHS.getReg());
BuildMI(*MBB, MI, DL, TII.get(BrKind)).addReg(RegB).addMBB(TargetBB);
BuildMI(*MBB, MI, DL, TII.get(BrKind))
.addReg(RegB, RegState::Kill)
.addMBB(TargetBB);

MI.eraseFromParent();
return MBB;
Expand Down

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