Fix for mclk/bclk divisors #8326 (IDFGH-6698)

[s-hadinger]

This is a first tentative to #8326

bclk_div is set to 32 which is the highest power of 2 possible for this hardware register (6 bits).

bclk target is sample_rate * I2S_LL_AD_BCK_FACTOR. I removed the additional factor 2 which looks erroneous with audio output.

[s-hadinger]

Tentative fix for espressif/arduino-esp32#5938

[s-hadinger]

Applying this patch locally makes Audio DAC working again.

Here are the new computed values:
sclk=160000000 mclk=1024000 bclk=32000 mclk_div=156 bclk_div=32

[L-KAYA]

Many thanks for fixing the DAC clock, I have checked it and it can work. But have you test this clock setting with ADC mode? It seems can't work for ADC mode

[s-hadinger]

No I haven't tested ADC mode.

[L-KAYA]

Oh sorry, don't mind ADC, it's my fault.

So now the bclk_div is the real bit_per_chan, for sclk=160000000 mclk=1024000 bclk=32000 mclk_div=156 bclk_div=32, we got 32 bit * 2 channel = 64 mclk ticks in one sample period. Do we need to fix the bclk_div to 32? Or set bclk_div equal to bit_per_chan dynamically, so that users can control this field.

FYI, while we are not using APLL, and set a low sample rate for ADC/DAC, the mclk_div will exceed its maximum value 255 (it has only 8 bit in reg), which can lead the clock go wrong.

[s-hadinger]

Thanks for the feedback. I suppose that mclk_div=156 is the maximum we can set to not override the 8 bits counter, then bclk_div can indeed be used to adjust.

[L-KAYA]

Thanks for the feedback. I suppose that mclk_div=156 is the maximum we can set to not override the 8 bits counter, then bclk_div can indeed be used to adjust.

Considering sometimes DAC will work together with ADC, 8 bits is not the best solution, because ADC needs 16 bits channel width to receive 12 bits width data. I think we need to use bit_per_chan as bclk_div and add mclk_div check for it.

This issue will be fixed recently, the commit in the PR will be involved, thanks for the contribution!

[Alvin1Zhang]

Thanks for your contribution, changes merged with 2f0e7e9

[dzanis]

This fix broke the I2S ADC, had to revert the old code back

[s-hadinger]

Can you give more details about the parameters you have been using?

[dzanis]

My board is ESP32-WROOM-32.
Current version IDF 4.4.1

I didn't use a DAC so I don't know how it behaves, but the ADC works with the wrong frequency to read samples. I recorded from a microphone and the sound turned out to be very slow.
My parameters for one I2S ADC channel

int _sampleRate = 16000;

i2s_config_t i2s_config = {
    .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN),
    .sample_rate = _sampleRate,
    .bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT,
    .channel_format = I2S_CHANNEL_FMT_ONLY_LEFT,
    .communication_format = I2S_COMM_FORMAT_STAND_I2S,
    .intr_alloc_flags = ESP_INTR_FLAG_LEVEL2,
    .dma_buf_count = 128,
    .dma_buf_len = 2,
    .use_apll = false
  };

I fixed it by returning the code with this condition to the compiler

#if ESP_IDF_VERSION > ESP_IDF_VERSION_VAL(3, 3, 5)
  #define I2S_LL_AD_BCK_FACTOR           (2)
  int bclk = _sampleRate * I2S_LL_AD_BCK_FACTOR * 2;
  int bclk_div = I2S_LL_AD_BCK_FACTOR;
  i2s_config.use_apll = true;
  i2s_config.fixed_mclk = bclk * bclk_div;
#endif

And the problem was solved, the samples are normal.
But I hope that this will be fixed, such a crutch is not very beautiful