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Fix RiscV installation/uninstallation #107
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SergioGasquez
merged 27 commits into
esp-rs:main
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SergioGasquez:fix/riscv-uninstall
Dec 23, 2022
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0ae42f5
fix: 🐛 Fix typo
SergioGasquez 1f8a04e
fix: 🐛 Fix riscv uninstallation
SergioGasquez e2c550f
fix: 🐛 Fix riscv uninstall logs
SergioGasquez caef1e1
chore: 🎨 Update RISC-V logs to make them consistent
SergioGasquez 70049af
feat: ✨ Use both `imc` and `imac` target for RISC-V targets
SergioGasquez d63b549
refactor: ♻️ Initial async
SergioGasquez 2ae93f8
refactor: ♻️ Use struct to store RiscV Target info so we can impl Ins…
SergioGasquez 4717922
refactor: ⚡️ Use RiscVTarget constructor
SergioGasquez c9fbf03
chore: ✨ Initial attemp to paralelize installations
SergioGasquez 8b2fcf9
feat: ✨ Spawn a task for every install
SergioGasquez b15b7bb
feat: ✨ Await only the len of to_install
SergioGasquez 039d70e
fix: 🐛 Add llvm to to_install
SergioGasquez ec65811
feat: ✨ Paralelize gcc installation
SergioGasquez a301fad
fix: 🐛 Fix receiving
SergioGasquez b0b338e
fix: 🐛 Remove TODO
SergioGasquez 26986b5
fix: 🐛 Remove stopwatch
SergioGasquez 5a322c6
fix: 🐛 Fix Windows build
SergioGasquez 6d16b3f
fix: 🐛 Fix riscv uninstallation
SergioGasquez d472f26
chore: 🎨 Update RISC-V logs to make them consistent
SergioGasquez da77129
fix: 🐛 Fix duplicated import
SergioGasquez adef0ba
feat: ✨ Use both `imc` and `imac` target for RISC-V targets
SergioGasquez 2d837b8
chore: 🎨 Update RISC-V logs to make them consistent
SergioGasquez e1fc141
Merge branch 'main' into fix/riscv-uninstall
SergioGasquez 3e729ed
fix: 🐛 Export variables even when reusing GCC installation
SergioGasquez 212a384
fix: 🐛 Return result instead of unwrapping
SergioGasquez 25cd4f2
fix: 🐛 Only install `riscv32-esp-elf` once
SergioGasquez c9306bd
fix: 🐛 Fix clippy
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Maybe a nicer way of handling this (which could be done in a separate PR) would be to implement some helpers on
Target
to determine the architecture. As we continue to add support for addition devices we're going to keep needing to chain expressions with||
here.Maybe if we do something like this:
We can then change this line (and the others like it) to something like this:
Just a thought, doesn't really matter right now but will likely clean things up in the future. If you don't like this idea then that is fine of course too 😁
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Thanks for the idea! It would definitely things scale better! I will address this on a different PR though. I also plan to install RISC-V GCC toolchain (
riscv32-esp-elf
) for ESP32-S2 and ESP32-S3 for the ULP coprocessor.