feat: ✨ Add ESP32-H2 support

README.md

@@ -179,7 +179,7 @@ Options:
           With this option, espup will skip GCC installation (it will be handled by esp-idf-sys), hence you won't be able to build no_std applications.
 
   -t, --targets <TARGETS>
-          Comma or space separated list of targets [esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,all]
+          Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c6,esp32h2,esp32s2,esp32s3,all]
 
           [default: all]
 

src/main.rs

@@ -90,7 +90,7 @@ pub struct InstallOpts {
     /// With this option, espup will skip GCC installation (it will be handled by esp-idf-sys), hence you won't be able to build no_std applications.
     #[arg(short = 's', long)]
     pub std: bool,
-    /// Comma or space separated list of targets [esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,all].
+    /// Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c6,esp32h2,esp32s2,esp32s3,all].
     #[arg(short = 't', long, default_value = "all", value_parser = parse_targets)]
     pub targets: HashSet<Target>,
     /// Xtensa Rust toolchain version.

src/targets.rs

@@ -11,16 +11,18 @@ use strum::{Display, EnumIter, EnumString, IntoEnumIterator};
 pub enum Target {
     /// Xtensa LX6 based dual core
     ESP32 = 0,
-    /// Xtensa LX7 based single core
-    ESP32S2,
-    /// Xtensa LX7 based dual core
-    ESP32S3,
     /// RISC-V based single core
     ESP32C2,
     /// RISC-V based single core
     ESP32C3,
     /// RISC-V based single core
     ESP32C6,
+    /// RISC-V based single core
+    ESP32H2,
+    /// Xtensa LX7 based single core
+    ESP32S2,
+    /// Xtensa LX7 based dual core
+    ESP32S3,
 }
 
 impl Target {
@@ -82,11 +84,12 @@ mod tests {
         ));
         let targets: HashSet<Target> = [
             Target::ESP32,
-            Target::ESP32S2,
-            Target::ESP32S3,
             Target::ESP32C2,
             Target::ESP32C3,
             Target::ESP32C6,
+            Target::ESP32H2,
+            Target::ESP32S2,
+            Target::ESP32S3,
         ]
         .into_iter()
         .collect();

src/toolchain/gcc.rs

@@ -163,7 +163,7 @@ pub fn get_gcc_name(target: &Target) -> String {
         Target::ESP32 => ESP32_GCC,
         Target::ESP32S2 => ESP32S2_GCC,
         Target::ESP32S3 => ESP32S3_GCC,
-        Target::ESP32C2 | Target::ESP32C3 | Target::ESP32C6 => RISCV_GCC,
+        Target::ESP32C2 | Target::ESP32C3 | Target::ESP32C6 | Target::ESP32H2 => RISCV_GCC,
     };
     toolchain.to_string()
 }