Add ESP32-C2 support

Cargo.toml

@@ -29,7 +29,7 @@ embedded-storage = "0.3.0"
 [target.riscv32imc-unknown-none-elf.dev-dependencies]
 esp32c3-hal = { version = "0.2.0" }
 riscv-rt = { version = "0.9.0" }
-riscv = { version = "0.8.0" }
+riscv = { version = "0.9.0" }
 esp-println = { version = "0.3.0", features = [ "esp32c3" ] }
 esp-backtrace = { git = "https://github.com/esp-rs/esp-backtrace.git", features = [ "esp32c3", "panic-handler", "exception-handler" ] }
 
@@ -55,6 +55,7 @@ esp-println = { version = "0.3.0", features = [ "esp32s3" ] }
 esp-backtrace = { git = "https://github.com/esp-rs/esp-backtrace.git", features = [ "esp32s3", "panic-handler", "exception-handler" ] }
 
 [features]
+esp32c2 = []
 esp32c3 = []
 esp32 = []
 esp32s2 = []

README.md

@@ -16,6 +16,16 @@ ESP32, ESP32-S2, ESP32-S3 and ESP32-C3 work
 
 `cargo "+nightly" run --example demo --features esp32c3 --target riscv32imc-unknown-none-elf`
 
+To run the example for ESP32-C2 you need to modify `Cargo-toml`, section `target.riscv32imc-unknown-none-elf.dev-dependencies` like this:
+
+```toml
+esp32c2-hal = { git = "https://github.com/esp-rs/esp-hal/", package = "esp32c2-hal" }
+riscv-rt = { version = "0.9.0" }
+riscv = { version = "0.9.0" }
+esp-println = { version = "0.3.0", features = [ "esp32c2" ] }
+esp-backtrace = { git = "https://github.com/esp-rs/esp-backtrace.git", features = [ "esp32c2", "panic-handler", "exception-handler" ] }
+```
+
 ## Important
 
 For ESP32 it is necessary to build with optimization level 2 or 3.

examples/demo.rs

@@ -14,13 +14,16 @@ use esp32s3_hal as hal;
 #[cfg(feature = "esp32c3")]
 use esp32c3_hal as hal;
 
+#[cfg(feature = "esp32c2")]
+use esp32c2_hal as hal;
+
 use hal::{clock::ClockControl, pac::Peripherals, prelude::*, timer::TimerGroup, Rtc};
 
 use esp_storage::FlashStorage;
 #[cfg(any(feature = "esp32", feature = "esp32s2", feature = "esp32s3"))]
 use xtensa_lx_rt::entry;
 
-#[cfg(feature = "esp32c3")]
+#[cfg(any(feature = "esp32c3", feature = "esp32c2"))]
 use riscv_rt::entry;
 
 use esp_backtrace as _;
@@ -48,20 +51,24 @@ fn main() -> ! {
         rtc.rwdt.disable();
     }
 
-    #[cfg(feature = "esp32c3")]
+    #[cfg(any(feature = "esp32c3", feature = "esp32c2"))]
     {
         let system = peripherals.SYSTEM.split();
         let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
 
         let mut rtc = Rtc::new(peripherals.RTC_CNTL);
         let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
         let mut wdt0 = timer_group0.wdt;
+
+        #[cfg(not(feature = "esp32c2"))]
         let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
+        #[cfg(not(feature = "esp32c2"))]
         let mut wdt1 = timer_group1.wdt;
 
         rtc.swd.disable();
         rtc.rwdt.disable();
         wdt0.disable();
+        #[cfg(not(feature = "esp32c2"))]
         wdt1.disable();
     }
 

src/esp32c2.rs

@@ -0,0 +1,36 @@
+const ESP_ROM_SPIFLASH_READ: u32 = 0x4000013c;
+const ESP_ROM_SPIFLASH_UNLOCK: u32 = 0x40000140;
+const ESP_ROM_SPIFLASH_ERASE_SECTOR: u32 = 0x40000130;
+const ESP_ROM_SPIFLASH_WRITE: u32 = 0x40000138;
+
+pub(crate) fn esp_rom_spiflash_read(src_addr: u32, data: *const u32, len: u32) -> i32 {
+    unsafe {
+        let esp_rom_spiflash_read: unsafe extern "C" fn(u32, *const u32, u32) -> i32 =
+            core::mem::transmute(ESP_ROM_SPIFLASH_READ);
+        esp_rom_spiflash_read(src_addr, data, len)
+    }
+}
+
+pub(crate) fn esp_rom_spiflash_unlock() -> i32 {
+    unsafe {
+        let esp_rom_spiflash_unlock: unsafe extern "C" fn() -> i32 =
+            core::mem::transmute(ESP_ROM_SPIFLASH_UNLOCK);
+        esp_rom_spiflash_unlock()
+    }
+}
+
+pub(crate) fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32 {
+    unsafe {
+        let esp_rom_spiflash_erase_sector: unsafe extern "C" fn(u32) -> i32 =
+            core::mem::transmute(ESP_ROM_SPIFLASH_ERASE_SECTOR);
+        esp_rom_spiflash_erase_sector(sector_number)
+    }
+}
+
+pub(crate) fn esp_rom_spiflash_write(dest_addr: u32, data: *const u8, len: u32) -> i32 {
+    unsafe {
+        let esp_rom_spiflash_write: unsafe extern "C" fn(u32, *const u8, u32) -> i32 =
+            core::mem::transmute(ESP_ROM_SPIFLASH_WRITE);
+        esp_rom_spiflash_write(dest_addr, data, len)
+    }
+}

src/lib.rs

@@ -2,6 +2,7 @@
 
 use embedded_storage::{ReadStorage, Storage};
 
+#[cfg_attr(feature = "esp32c2", path = "esp32c2.rs")]
 #[cfg_attr(feature = "esp32c3", path = "esp32c3.rs")]
 #[cfg_attr(feature = "esp32", path = "esp32.rs")]
 #[cfg_attr(feature = "esp32s2", path = "esp32s2.rs")]