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Merged
merged 2 commits into from
May 27, 2024
Merged

Update svd2rust and other xtask dependencies, regenerate all PACs #251

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6d13866
Update `svd2rust` and other `xtask` dependencies
jessebraham May 27, 2024
b666c18
Regenerate all PACS
jessebraham May 27, 2024
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8 changes: 1 addition & 7 deletions esp32/src/aes/endian.rs
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Expand Up @@ -17,16 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ENDIAN")
.field("endian", &format_args!("{}", self.endian().bits()))
.field("endian", &self.endian())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:1 - Endianness selection register. See Table 22-2 for details."]
#[inline(always)]
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10 changes: 1 addition & 9 deletions esp32/src/aes/idle.rs
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Expand Up @@ -12,15 +12,7 @@ impl R {
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IDLE")
.field("idle", &format_args!("{}", self.idle().bit()))
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<IDLE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
f.debug_struct("IDLE").field("idle", &self.idle()).finish()
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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10 changes: 1 addition & 9 deletions esp32/src/aes/key.rs
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Expand Up @@ -16,15 +16,7 @@ impl R {
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("KEY")
.field("key", &format_args!("{}", self.key().bits()))
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
f.debug_struct("KEY").field("key", &self.key()).finish()
}
}
impl W {
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10 changes: 1 addition & 9 deletions esp32/src/aes/mode.rs
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Expand Up @@ -16,15 +16,7 @@ impl R {
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MODE")
.field("mode", &format_args!("{}", self.mode().bits()))
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
f.debug_struct("MODE").field("mode", &self.mode()).finish()
}
}
impl W {
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10 changes: 1 addition & 9 deletions esp32/src/aes/text.rs
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Expand Up @@ -16,15 +16,7 @@ impl R {
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TEXT")
.field("text", &format_args!("{}", self.text().bits()))
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<TEXT_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
f.debug_struct("TEXT").field("text", &self.text()).finish()
}
}
impl W {
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71 changes: 13 additions & 58 deletions esp32/src/apb_ctrl/apb_saradc_ctrl.rs
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Expand Up @@ -125,67 +125,22 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC_CTRL")
.field(
"saradc_start_force",
&format_args!("{}", self.saradc_start_force().bit()),
)
.field(
"saradc_start",
&format_args!("{}", self.saradc_start().bit()),
)
.field(
"saradc_sar2_mux",
&format_args!("{}", self.saradc_sar2_mux().bit()),
)
.field(
"saradc_work_mode",
&format_args!("{}", self.saradc_work_mode().bits()),
)
.field(
"saradc_sar_sel",
&format_args!("{}", self.saradc_sar_sel().bit()),
)
.field(
"saradc_sar_clk_gated",
&format_args!("{}", self.saradc_sar_clk_gated().bit()),
)
.field(
"saradc_sar_clk_div",
&format_args!("{}", self.saradc_sar_clk_div().bits()),
)
.field(
"saradc_sar1_patt_len",
&format_args!("{}", self.saradc_sar1_patt_len().bits()),
)
.field(
"saradc_sar2_patt_len",
&format_args!("{}", self.saradc_sar2_patt_len().bits()),
)
.field(
"saradc_sar1_patt_p_clear",
&format_args!("{}", self.saradc_sar1_patt_p_clear().bit()),
)
.field(
"saradc_sar2_patt_p_clear",
&format_args!("{}", self.saradc_sar2_patt_p_clear().bit()),
)
.field(
"saradc_data_sar_sel",
&format_args!("{}", self.saradc_data_sar_sel().bit()),
)
.field(
"saradc_data_to_i2s",
&format_args!("{}", self.saradc_data_to_i2s().bit()),
)
.field("saradc_start_force", &self.saradc_start_force())
.field("saradc_start", &self.saradc_start())
.field("saradc_sar2_mux", &self.saradc_sar2_mux())
.field("saradc_work_mode", &self.saradc_work_mode())
.field("saradc_sar_sel", &self.saradc_sar_sel())
.field("saradc_sar_clk_gated", &self.saradc_sar_clk_gated())
.field("saradc_sar_clk_div", &self.saradc_sar_clk_div())
.field("saradc_sar1_patt_len", &self.saradc_sar1_patt_len())
.field("saradc_sar2_patt_len", &self.saradc_sar2_patt_len())
.field("saradc_sar1_patt_p_clear", &self.saradc_sar1_patt_p_clear())
.field("saradc_sar2_patt_p_clear", &self.saradc_sar2_patt_p_clear())
.field("saradc_data_sar_sel", &self.saradc_data_sar_sel())
.field("saradc_data_to_i2s", &self.saradc_data_to_i2s())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_CTRL_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
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26 changes: 4 additions & 22 deletions esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
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Expand Up @@ -44,31 +44,13 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC_CTRL2")
.field(
"saradc_meas_num_limit",
&format_args!("{}", self.saradc_meas_num_limit().bit()),
)
.field(
"saradc_max_meas_num",
&format_args!("{}", self.saradc_max_meas_num().bits()),
)
.field(
"saradc_sar1_inv",
&format_args!("{}", self.saradc_sar1_inv().bit()),
)
.field(
"saradc_sar2_inv",
&format_args!("{}", self.saradc_sar2_inv().bit()),
)
.field("saradc_meas_num_limit", &self.saradc_meas_num_limit())
.field("saradc_max_meas_num", &self.saradc_max_meas_num())
.field("saradc_sar1_inv", &self.saradc_sar1_inv())
.field("saradc_sar2_inv", &self.saradc_sar2_inv())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_CTRL2_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
Expand Down
26 changes: 4 additions & 22 deletions esp32/src/apb_ctrl/apb_saradc_fsm.rs
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Expand Up @@ -44,31 +44,13 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC_FSM")
.field(
"saradc_rstb_wait",
&format_args!("{}", self.saradc_rstb_wait().bits()),
)
.field(
"saradc_standby_wait",
&format_args!("{}", self.saradc_standby_wait().bits()),
)
.field(
"saradc_start_wait",
&format_args!("{}", self.saradc_start_wait().bits()),
)
.field(
"saradc_sample_cycle",
&format_args!("{}", self.saradc_sample_cycle().bits()),
)
.field("saradc_rstb_wait", &self.saradc_rstb_wait())
.field("saradc_standby_wait", &self.saradc_standby_wait())
.field("saradc_start_wait", &self.saradc_start_wait())
.field("saradc_sample_cycle", &self.saradc_sample_cycle())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_FSM_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
Expand Down
11 changes: 1 addition & 10 deletions esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
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Expand Up @@ -17,19 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC_SAR1_PATT_TAB")
.field(
"saradc_sar1_patt_tab1",
&format_args!("{}", self.saradc_sar1_patt_tab1().bits()),
)
.field("saradc_sar1_patt_tab1", &self.saradc_sar1_patt_tab1())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_SAR1_PATT_TAB_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
#[inline(always)]
Expand Down
11 changes: 1 addition & 10 deletions esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
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Expand Up @@ -17,19 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_SARADC_SAR2_PATT_TAB")
.field(
"saradc_sar2_patt_tab1",
&format_args!("{}", self.saradc_sar2_patt_tab1().bits()),
)
.field("saradc_sar2_patt_tab1", &self.saradc_sar2_patt_tab1())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_SAR2_PATT_TAB_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
#[inline(always)]
Expand Down
11 changes: 1 addition & 10 deletions esp32/src/apb_ctrl/apll_tick_conf.rs
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Expand Up @@ -17,19 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APLL_TICK_CONF")
.field(
"apll_tick_num",
&format_args!("{}", self.apll_tick_num().bits()),
)
.field("apll_tick_num", &self.apll_tick_num())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<APLL_TICK_CONF_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
Expand Down
11 changes: 1 addition & 10 deletions esp32/src/apb_ctrl/ck8m_tick_conf.rs
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Expand Up @@ -17,19 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CK8M_TICK_CONF")
.field(
"ck8m_tick_num",
&format_args!("{}", self.ck8m_tick_num().bits()),
)
.field("ck8m_tick_num", &self.ck8m_tick_num())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<CK8M_TICK_CONF_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
Expand Down
10 changes: 1 addition & 9 deletions esp32/src/apb_ctrl/date.rs
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Expand Up @@ -16,15 +16,7 @@ impl R {
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DATE")
.field("date", &format_args!("{}", self.date().bits()))
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
f.debug_struct("DATE").field("date", &self.date()).finish()
}
}
impl W {
Expand Down
11 changes: 1 addition & 10 deletions esp32/src/apb_ctrl/pll_tick_conf.rs
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Expand Up @@ -17,19 +17,10 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PLL_TICK_CONF")
.field(
"pll_tick_num",
&format_args!("{}", self.pll_tick_num().bits()),
)
.field("pll_tick_num", &self.pll_tick_num())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<PLL_TICK_CONF_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
Expand Down
25 changes: 5 additions & 20 deletions esp32/src/apb_ctrl/sysclk_conf.rs
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Expand Up @@ -53,29 +53,14 @@ impl R {
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCLK_CONF")
.field(
"pre_div_cnt",
&format_args!("{}", self.pre_div_cnt().bits()),
)
.field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
.field("clk_en", &format_args!("{}", self.clk_en().bit()))
.field(
"rst_tick_cnt",
&format_args!("{}", self.rst_tick_cnt().bit()),
)
.field(
"quick_clk_chng",
&format_args!("{}", self.quick_clk_chng().bit()),
)
.field("pre_div_cnt", &self.pre_div_cnt())
.field("clk_320m_en", &self.clk_320m_en())
.field("clk_en", &self.clk_en())
.field("rst_tick_cnt", &self.rst_tick_cnt())
.field("quick_clk_chng", &self.quick_clk_chng())
.finish()
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
Expand Down
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