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Option to configure rx/tx fifo sizes and queue size #1827

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Option to configure rx/tx fifo sizes and queue size

Option to configure rx/tx fifo sizes and queue size #1827

Triggered via push August 8, 2023 17:09
@ivmarkovivmarkov
pushed 24543de
master
Status Failure
Total duration 8m 52s
Artifacts –

ci.yml

on: push
Matrix: Compile
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8 errors
Compile (riscv32imc-esp-espidf, release/v5.1)
Process completed with exit code 101.
Compile (riscv32imc-esp-espidf, release/v4.4)
Process completed with exit code 101.
Compile (xtensa-esp32s2-espidf, release/v5.1)
Process completed with exit code 101.
Compile (xtensa-esp32-espidf, release/v5.1)
Process completed with exit code 101.
Compile (xtensa-esp32s3-espidf, release/v5.1)
Process completed with exit code 101.
Compile (xtensa-esp32-espidf, release/v4.4)
Process completed with exit code 101.
Compile (xtensa-esp32s3-espidf, release/v4.4)
Process completed with exit code 101.
Compile (xtensa-esp32s2-espidf, release/v4.4)
Process completed with exit code 101.