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Remove Gpio type aliasses #2073

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Sep 4, 2024
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Remove Gpio type aliasses #2073

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845b0c8
Remove Gpio type aliasses
bugadani Sep 4, 2024
6bdbe07
Clean up examples
bugadani Sep 4, 2024
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1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Expand Up @@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

- Removed `NoPinType` in favour of `DummyPin`. (#2068)
- Removed the `async`, `embedded-hal-02`, `embedded-hal`, `embedded-io`, `embedded-io-async`, and `ufmt` features (#2070)
- Removed the `GpioN` type aliasses. Use `GpioPin<N>` instead. (#2073)

## [0.20.1] - 2024-08-30

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4 changes: 4 additions & 0 deletions esp-hal/MIGRATING-0.20.md
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Expand Up @@ -35,3 +35,7 @@ Instead of manually grabbing peripherals and setting up clocks, you should now c
// ...
}
```

## GPIO changes

The `GpioN` type aliasses are no longer available. You can use `GpioPin<N>` instead.
36 changes: 18 additions & 18 deletions esp-hal/src/analog/adc/esp32.rs
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Expand Up @@ -359,29 +359,29 @@ where
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio36, 0), // Alt. name: SENSOR_VP
(Gpio37, 1), // Alt. name: SENSOR_CAPP
(Gpio38, 2), // Alt. name: SENSOR_CAPN
(Gpio39, 3), // Alt. name: SENSOR_VN
(Gpio33, 4), // Alt. name: 32K_XP
(Gpio32, 5), // Alt. name: 32K_XN
(Gpio34, 6), // Alt. name: VDET_1
(Gpio35, 7), // Alt. name: VDET_2
(GpioPin<36>, 0), // Alt. name: SENSOR_VP
(GpioPin<37>, 1), // Alt. name: SENSOR_CAPP
(GpioPin<38>, 2), // Alt. name: SENSOR_CAPN
(GpioPin<39>, 3), // Alt. name: SENSOR_VN
(GpioPin<33>, 4), // Alt. name: 32K_XP
(GpioPin<32>, 5), // Alt. name: 32K_XN
(GpioPin<34>, 6), // Alt. name: VDET_1
(GpioPin<35>, 7), // Alt. name: VDET_2
]
}

crate::analog::adc::impl_adc_interface! {
ADC2 [
(Gpio4, 0),
(Gpio0, 1),
(Gpio2, 2),
(Gpio15, 3), // Alt. name: MTDO
(Gpio13, 4), // Alt. name: MTCK
(Gpio12, 5), // Alt. name: MTDI
(Gpio14, 6), // Alt. name: MTMS
(Gpio27, 7),
(Gpio25, 8),
(Gpio26, 9),
(GpioPin<4>, 0),
(GpioPin<0>, 1),
(GpioPin<2>, 2),
(GpioPin<15>, 3), // Alt. name: MTDO
(GpioPin<13>, 4), // Alt. name: MTCK
(GpioPin<12>, 5), // Alt. name: MTDI
(GpioPin<14>, 6), // Alt. name: MTMS
(GpioPin<27>, 7),
(GpioPin<25>, 8),
(GpioPin<26>, 9),
]
}
}
6 changes: 3 additions & 3 deletions esp-hal/src/analog/adc/mod.rs
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Expand Up @@ -252,14 +252,14 @@ trait AdcCalEfuse {

macro_rules! impl_adc_interface {
($adc:ident [
$( ($pin:ident, $channel:expr) ,)+
$( (GpioPin<$pin:literal>, $channel:expr) ,)+
]) => {
$(
impl $crate::analog::adc::AdcChannel for crate::gpio::$pin {
impl $crate::analog::adc::AdcChannel for crate::gpio::GpioPin<$pin> {
const CHANNEL: u8 = $channel;
}

impl embedded_hal_02::adc::Channel<crate::peripherals::$adc> for crate::gpio::$pin {
impl embedded_hal_02::adc::Channel<crate::peripherals::$adc> for crate::gpio::GpioPin<$pin> {
type ID = u8;

fn channel() -> u8 { $channel }
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46 changes: 23 additions & 23 deletions esp-hal/src/analog/adc/riscv.rs
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Expand Up @@ -548,11 +548,11 @@ where
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio0, 0),
(Gpio1, 1),
(Gpio2, 2),
(Gpio3, 3),
(Gpio4, 4),
(GpioPin<0>, 0),
(GpioPin<1>, 1),
(GpioPin<2>, 2),
(GpioPin<3>, 3),
(GpioPin<4>, 4),
]
}
}
Expand All @@ -561,17 +561,17 @@ mod adc_implementation {
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio0, 0),
(Gpio1, 1),
(Gpio2, 2),
(Gpio3, 3),
(Gpio4, 4),
(GpioPin<0>, 0),
(GpioPin<1>, 1),
(GpioPin<2>, 2),
(GpioPin<3>, 3),
(GpioPin<4>, 4),
]
}

crate::analog::adc::impl_adc_interface! {
ADC2 [
(Gpio5, 0),
(GpioPin<5>, 0),
]
}
}
Expand All @@ -580,13 +580,13 @@ mod adc_implementation {
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio0, 0),
(Gpio1, 1),
(Gpio2, 2),
(Gpio3, 3),
(Gpio4, 4),
(Gpio5, 5),
(Gpio6, 6),
(GpioPin<0>, 0),
(GpioPin<1>, 1),
(GpioPin<2>, 2),
(GpioPin<3>, 3),
(GpioPin<4>, 4),
(GpioPin<5>, 5),
(GpioPin<6>, 6),
]
}
}
Expand All @@ -595,11 +595,11 @@ mod adc_implementation {
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio1, 0),
(Gpio2, 1),
(Gpio3, 2),
(Gpio4, 3),
(Gpio5, 4),
(GpioPin<1>, 0),
(GpioPin<2>, 1),
(GpioPin<3>, 2),
(GpioPin<4>, 3),
(GpioPin<5>, 4),
]
}
}
40 changes: 20 additions & 20 deletions esp-hal/src/analog/adc/xtensa.rs
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Expand Up @@ -607,31 +607,31 @@ where
mod adc_implementation {
crate::analog::adc::impl_adc_interface! {
ADC1 [
(Gpio1, 0),
(Gpio2, 1),
(Gpio3, 2),
(Gpio4, 3),
(Gpio5, 4),
(Gpio6, 5),
(Gpio7, 6),
(Gpio8, 7),
(Gpio9, 8),
(Gpio10, 9),
(GpioPin<1>, 0),
(GpioPin<2>, 1),
(GpioPin<3>, 2),
(GpioPin<4>, 3),
(GpioPin<5>, 4),
(GpioPin<6>, 5),
(GpioPin<7>, 6),
(GpioPin<8>, 7),
(GpioPin<9>, 8),
(GpioPin<10>, 9),
]
}

crate::analog::adc::impl_adc_interface! {
ADC2 [
(Gpio11, 0),
(Gpio12, 1),
(Gpio13, 2),
(Gpio14, 3),
(Gpio15, 4),
(Gpio16, 5),
(Gpio17, 6),
(Gpio18, 7),
(Gpio19, 8),
(Gpio20, 9),
(GpioPin<11>, 0),
(GpioPin<12>, 1),
(GpioPin<13>, 2),
(GpioPin<14>, 3),
(GpioPin<15>, 4),
(GpioPin<16>, 5),
(GpioPin<17>, 6),
(GpioPin<18>, 7),
(GpioPin<19>, 8),
(GpioPin<20>, 9),
]
}
}
8 changes: 4 additions & 4 deletions esp-hal/src/analog/dac.rs
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Expand Up @@ -51,11 +51,11 @@ use crate::{
// reason, we will type alias the pins for ease of use later in this module:
cfg_if::cfg_if! {
if #[cfg(esp32)] {
type Dac1Gpio = gpio::Gpio25;
type Dac2Gpio = gpio::Gpio26;
type Dac1Gpio = gpio::GpioPin<25>;
type Dac2Gpio = gpio::GpioPin<26>;
} else if #[cfg(esp32s2)] {
type Dac1Gpio = gpio::Gpio17;
type Dac2Gpio = gpio::Gpio18;
type Dac1Gpio = gpio::GpioPin<17>;
type Dac2Gpio = gpio::GpioPin<18>;
}
}

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7 changes: 1 addition & 6 deletions esp-hal/src/gpio/mod.rs
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Expand Up @@ -1418,15 +1418,10 @@ macro_rules! gpio {
)+
}

$(
#[doc = concat!("Alias for GpioPin<MODE, ", $gpionum, ">")]
pub type [<Gpio $gpionum >] = GpioPin<$gpionum>;
)+

#[doc(hidden)]
pub enum ErasedPin {
$(
[<Gpio $gpionum >]([<Gpio $gpionum >]),
[<Gpio $gpionum >](GpioPin<$gpionum>),
)+
}

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4 changes: 2 additions & 2 deletions esp-hal/src/soc/esp32s2/gpio.rs
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Expand Up @@ -443,5 +443,5 @@ impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
}

// implement marker traits on USB pins
impl crate::otg_fs::UsbDm for Gpio19 {}
impl crate::otg_fs::UsbDp for Gpio20 {}
impl crate::otg_fs::UsbDm for GpioPin<19> {}
impl crate::otg_fs::UsbDp for GpioPin<20> {}
4 changes: 2 additions & 2 deletions esp-hal/src/soc/esp32s3/gpio.rs
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Expand Up @@ -493,5 +493,5 @@ impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
}

// implement marker traits on USB pins
impl crate::otg_fs::UsbDm for Gpio19 {}
impl crate::otg_fs::UsbDp for Gpio20 {}
impl crate::otg_fs::UsbDm for GpioPin<19> {}
impl crate::otg_fs::UsbDp for GpioPin<20> {}
28 changes: 14 additions & 14 deletions esp-hal/src/uart.rs
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Expand Up @@ -161,59 +161,59 @@ cfg_if::cfg_if! {
if #[cfg(esp32)] {
/// Default TX pin for UART0 on ESP32.
/// Corresponds to GPIO1.
pub type DefaultTxPin = crate::gpio::Gpio1;
pub type DefaultTxPin = crate::gpio::GpioPin<1>;

/// Default RX pin for UART0 on ESP32.
/// Corresponds to GPIO3.
pub type DefaultRxPin = crate::gpio::Gpio3;
pub type DefaultRxPin = crate::gpio::GpioPin<3>;
} else if #[cfg(esp32c2)] {
/// Default TX pin for UART0 on ESP32-C2.
/// Corresponds to GPIO20.
pub type DefaultTxPin = crate::gpio::Gpio20;
pub type DefaultTxPin = crate::gpio::GpioPin<20>;

/// Default RX pin for UART0 on ESP32-C2.
/// Corresponds to GPIO19.
pub type DefaultRxPin = crate::gpio::Gpio19;
pub type DefaultRxPin = crate::gpio::GpioPin<19>;
} else if #[cfg(esp32c3)] {
/// Default TX pin for UART0 on ESP32-C3.
/// Corresponds to GPIO21.
pub type DefaultTxPin = crate::gpio::Gpio21;
pub type DefaultTxPin = crate::gpio::GpioPin<21>;

/// Default RX pin for UART0 on ESP32-C3.
/// Corresponds to GPIO20.
pub type DefaultRxPin = crate::gpio::Gpio20;
pub type DefaultRxPin = crate::gpio::GpioPin<20>;
} else if #[cfg(esp32c6)] {
/// Default TX pin for UART0 on ESP32-C6.
/// Corresponds to GPIO16.
pub type DefaultTxPin = crate::gpio::Gpio16;
pub type DefaultTxPin = crate::gpio::GpioPin<16>;

/// Default RX pin for UART0 on ESP32-C6.
/// Corresponds to GPIO17.
pub type DefaultRxPin = crate::gpio::Gpio17;
pub type DefaultRxPin = crate::gpio::GpioPin<17>;
} else if #[cfg(esp32h2)] {
/// Default TX pin for UART0 on ESP32-H2.
/// Corresponds to GPIO24.
pub type DefaultTxPin = crate::gpio::Gpio24;
pub type DefaultTxPin = crate::gpio::GpioPin<24>;

/// Default RX pin for UART0 on ESP32-H2.
/// Corresponds to GPIO23.
pub type DefaultRxPin = crate::gpio::Gpio23;
pub type DefaultRxPin = crate::gpio::GpioPin<23>;
} else if #[cfg(esp32s2)] {
/// Default TX pin for UART0 on ESP32-S2.
/// Corresponds to GPIO43.
pub type DefaultTxPin = crate::gpio::Gpio43;
pub type DefaultTxPin = crate::gpio::GpioPin<43>;

/// Default RX pin for UART0 on ESP32-S2.
/// Corresponds to GPIO44.
pub type DefaultRxPin = crate::gpio::Gpio44;
pub type DefaultRxPin = crate::gpio::GpioPin<44>;
} else if #[cfg(esp32s3)] {
/// Default TX pin for UART0 on ESP32-S3.
/// Corresponds to GPIO43.
pub type DefaultTxPin = crate::gpio::Gpio43;
pub type DefaultTxPin = crate::gpio::GpioPin<43>;

/// Default RX pin for UART0 on ESP32-S3.
/// Corresponds to GPIO44.
pub type DefaultRxPin = crate::gpio::Gpio44;
pub type DefaultRxPin = crate::gpio::GpioPin<44>;
}
}

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4 changes: 2 additions & 2 deletions examples/src/bin/embassy_rmt_rx.rs
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Expand Up @@ -13,7 +13,7 @@ use embassy_executor::Spawner;
use embassy_time::{Duration, Timer};
use esp_backtrace as _;
use esp_hal::{
gpio::{Gpio5, Io, Level, Output},
gpio::{GpioPin, Io, Level, Output},
prelude::*,
rmt::{asynch::RxChannelAsync, PulseCode, Rmt, RxChannelConfig, RxChannelCreatorAsync},
timer::timg::TimerGroup,
Expand All @@ -26,7 +26,7 @@ const WIDTH: usize = 80;
compile_error!("Run this example in release mode");

#[embassy_executor::task]
async fn signal_task(mut pin: Output<'static, Gpio5>) {
async fn signal_task(mut pin: Output<'static, GpioPin<5>>) {
loop {
for _ in 0..10 {
pin.toggle();
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8 changes: 5 additions & 3 deletions examples/src/bin/gpio_interrupt.rs
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Expand Up @@ -17,19 +17,21 @@ use critical_section::Mutex;
use esp_backtrace as _;
use esp_hal::{
delay::Delay,
gpio::{self, Event, Input, Io, Level, Output, Pull},
gpio::{Event, GpioPin, Input, Io, Level, Output, Pull},
macros::ram,
prelude::*,
};

cfg_if::cfg_if! {
if #[cfg(any(feature = "esp32", feature = "esp32s2", feature = "esp32s3"))] {
static BUTTON: Mutex<RefCell<Option<Input<gpio::Gpio0>>>> = Mutex::new(RefCell::new(None));
const BUTTON_PIN: u8 = 0;
} else {
static BUTTON: Mutex<RefCell<Option<Input<gpio::Gpio9>>>> = Mutex::new(RefCell::new(None));
const BUTTON_PIN: u8 = 9;
}
}

static BUTTON: Mutex<RefCell<Option<Input<GpioPin<BUTTON_PIN>>>>> = Mutex::new(RefCell::new(None));

#[entry]
fn main() -> ! {
let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default());
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