Completely remove pac references in hal drivers (#309)

* Peripheral ref/sha (#312) * Add SHA to list of peripherals to be created * Refactor SHA peripheral to use PeripheralRef * Update SHA examples to get them building again * Fix async time drivers * Fix usb otg * Fix s3 Co-authored-by: Jesse Braham <[email protected]>
esp-rs · Dec 14, 2022 · 3a57eb9 · 3a57eb9
1 parent 220f812
commit 3a57eb9
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Showing 54 changed files with 243 additions and 232 deletions.
diff --git a/esp-hal-common/src/analog/adc/esp32.rs b/esp-hal-common/src/analog/adc/esp32.rs
@@ -4,7 +4,7 @@ use embedded_hal::adc::{Channel, OneShot};
 
 use crate::{
     analog::{ADC1, ADC2},
-    pac::{RTCIO, SENS},
+    peripherals::{RTCIO, SENS},
 };
 
 /// The sampling/readout resolution of the ADC

diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs
@@ -6,7 +6,7 @@ use embedded_hal::adc::{Channel, OneShot};
 use crate::analog::ADC2;
 use crate::{
     analog::ADC1,
-    pac::APB_SARADC,
+    peripherals::APB_SARADC,
     system::{Peripheral, PeripheralClockControl},
 };
 

diff --git a/esp-hal-common/src/analog/adc/xtensa.rs b/esp-hal-common/src/analog/adc/xtensa.rs
@@ -4,7 +4,7 @@ use embedded_hal::adc::{Channel, OneShot};
 
 use crate::{
     analog::{ADC1, ADC2},
-    pac::{APB_SARADC, SENS},
+    peripherals::{APB_SARADC, SENS},
 };
 
 /// The sampling/readout resolution of the ADC

diff --git a/esp-hal-common/src/analog/dac.rs b/esp-hal-common/src/analog/dac.rs
@@ -1,4 +1,4 @@
-use crate::pac::{RTCIO, SENS};
+use crate::peripherals::{RTCIO, SENS};
 
 pub trait DAC {
     fn write(&mut self, value: u8);

diff --git a/esp-hal-common/src/analog/mod.rs b/esp-hal-common/src/analog/mod.rs
@@ -11,7 +11,7 @@ cfg_if::cfg_if! {
     if #[cfg(any(esp32, esp32s2, esp32s3))] {
         use core::marker::PhantomData;
 
-        use crate::pac::SENS;
+        use crate::peripherals::SENS;
 
         pub struct ADC1 {
             _private: PhantomData<()>,
@@ -65,7 +65,7 @@ cfg_if::cfg_if! {
     if #[cfg(esp32c3)] {
         use core::marker::PhantomData;
 
-        use crate::pac::APB_SARADC;
+        use crate::peripherals::APB_SARADC;
 
         pub struct ADC1 {
             _private: PhantomData<()>,
@@ -103,7 +103,7 @@ cfg_if::cfg_if! {
     if #[cfg(esp32c2)] {
         use core::marker::PhantomData;
 
-        use crate::pac::APB_SARADC;
+        use crate::peripherals::APB_SARADC;
 
         pub struct ADC1 {
             _private: PhantomData<()>,

diff --git a/esp-hal-common/src/clocks_ll/esp32.rs b/esp-hal-common/src/clocks_ll/esp32.rs
@@ -39,8 +39,8 @@ const I2C_BBPLL_OC_DIV_7_0: u32 = 3;
 const I2C_BBPLL_OC_DCUR: u32 = 5;
 
 pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) {
-    let efuse = unsafe { &*crate::pac::EFUSE::ptr() };
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     unsafe {
         let rtc_cntl_dbias_hp_volt: u32 =
@@ -201,7 +201,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
 }
 
 pub(crate) fn esp32_rtc_bbpll_enable() {
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     unsafe {
         rtc_cntl.options0.modify(|_, w| {
@@ -261,8 +261,8 @@ unsafe fn i2c_writereg_rtc(block: u32, block_hostid: u32, reg_add: u32, indata:
 }
 
 pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
-    let apb_cntl = unsafe { &*crate::pac::APB_CTRL::ptr() };
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let apb_cntl = unsafe { &*crate::peripherals::APB_CTRL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     unsafe {
         let value = (((freq.hz()) >> 12) & UINT16_MAX) | ((((freq.hz()) >> 12) & UINT16_MAX) << 16);
@@ -292,9 +292,9 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
 }
 
 pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) {
-    let efuse = unsafe { &*crate::pac::EFUSE::ptr() };
-    let dport = unsafe { &*crate::pac::DPORT::ptr() };
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() };
+    let dport = unsafe { &*crate::peripherals::DPORT::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     unsafe {
         const RTC_CNTL_DBIAS_1V25: u32 = 7;

diff --git a/esp-hal-common/src/clocks_ll/esp32c2.rs b/esp-hal-common/src/clocks_ll/esp32c2.rs
@@ -39,7 +39,7 @@ const I2C_MST_BBPLL_STOP_FORCE_HIGH: u32 = 1 << 2;
 const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 3;
 
 pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllClock) {
-    let system = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         let div_ref: u32;
@@ -112,7 +112,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
 }
 
 pub(crate) fn esp32c2_rtc_bbpll_enable() {
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     rtc_cntl.options0.modify(|_, w| {
         w.bb_i2c_force_pd()
@@ -125,7 +125,7 @@ pub(crate) fn esp32c2_rtc_bbpll_enable() {
 }
 
 pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         ets_update_cpu_frequency(freq.mhz());
@@ -148,7 +148,7 @@ pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
 }
 
 pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         system_control
@@ -165,7 +165,7 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
 }
 
 pub(crate) fn esp32c2_rtc_apb_freq_update(apb_freq: ApbClock) {
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     let value = ((apb_freq.hz() >> 12) & u16::MAX as u32)
         | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16);

diff --git a/esp-hal-common/src/clocks_ll/esp32c3.rs b/esp-hal-common/src/clocks_ll/esp32c3.rs
@@ -43,7 +43,7 @@ const I2C_MST_BBPLL_STOP_FORCE_HIGH: u32 = 1 << 3;
 const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 2;
 
 pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) {
-    let system = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         let div_ref: u32;
@@ -173,7 +173,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
 }
 
 pub(crate) fn esp32c3_rtc_bbpll_enable() {
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     rtc_cntl.options0.modify(|_, w| {
         w.bb_i2c_force_pd()
@@ -186,7 +186,7 @@ pub(crate) fn esp32c3_rtc_bbpll_enable() {
 }
 
 pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         ets_update_cpu_frequency(freq.mhz());
@@ -209,7 +209,7 @@ pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
 }
 
 pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::ptr() };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
     unsafe {
         system_control
@@ -226,7 +226,7 @@ pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
 }
 
 pub(crate) fn esp32c3_rtc_apb_freq_update(apb_freq: ApbClock) {
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
     let value = ((apb_freq.hz() >> 12) & u16::MAX as u32)
         | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16);
 

diff --git a/esp-hal-common/src/clocks_ll/esp32s2.rs b/esp-hal-common/src/clocks_ll/esp32s2.rs
@@ -11,8 +11,8 @@ const DIG_DBIAS_80M_160M: u32 = RTC_CNTL_DBIAS_1V25;
 const DIG_DBIAS_240M: u32 = RTC_CNTL_DBIAS_1V25;
 
 pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::PTR };
-    let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::PTR };
+    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
 
     unsafe {
         system_control

diff --git a/esp-hal-common/src/clocks_ll/esp32s3.rs b/esp-hal-common/src/clocks_ll/esp32s3.rs
@@ -1,7 +1,7 @@
 use crate::clock::CpuClock;
 
 pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
-    let system_control = unsafe { &*crate::pac::SYSTEM::PTR };
+    let system_control = unsafe { &*crate::peripherals::SYSTEM::PTR };
 
     unsafe {
         system_control

diff --git a/esp-hal-common/src/cpu_control/esp32.rs b/esp-hal-common/src/cpu_control/esp32.rs
@@ -33,7 +33,7 @@ pub struct CpuControl {
 }
 
 unsafe fn internal_park_core(core: Cpu) {
-    let rtc_control = crate::pac::RTC_CNTL::PTR;
+    let rtc_control = crate::peripherals::RTC_CNTL::PTR;
     let rtc_control = &*rtc_control;
 
     match core {
@@ -70,7 +70,7 @@ impl CpuControl {
 
     /// Unpark the given core
     pub fn unpark_core(&mut self, core: Cpu) {
-        let rtc_control = crate::pac::RTC_CNTL::PTR;
+        let rtc_control = crate::peripherals::RTC_CNTL::PTR;
         let rtc_control = unsafe { &*rtc_control };
 
         match core {
@@ -94,7 +94,7 @@ impl CpuControl {
     }
 
     fn flush_cache(&mut self, core: Cpu) {
-        let dport_control = crate::pac::DPORT::PTR;
+        let dport_control = crate::peripherals::DPORT::PTR;
         let dport_control = unsafe { &*dport_control };
 
         match core {
@@ -139,7 +139,7 @@ impl CpuControl {
     fn enable_cache(&mut self, core: Cpu) {
         let spi0 = unsafe { &(*crate::peripherals::SPI0::ptr()) };
 
-        let dport_control = crate::pac::DPORT::PTR;
+        let dport_control = crate::peripherals::DPORT::PTR;
         let dport_control = unsafe { &*dport_control };
 
         match core {
@@ -191,7 +191,7 @@ impl CpuControl {
         &mut self,
         entry: &mut (dyn FnMut() + Send),
     ) -> Result<AppCoreGuard, Error> {
-        let dport_control = crate::pac::DPORT::PTR;
+        let dport_control = crate::peripherals::DPORT::PTR;
         let dport_control = unsafe { &*dport_control };
 
         if !xtensa_lx::is_debugger_attached()

diff --git a/esp-hal-common/src/cpu_control/esp32s3.rs b/esp-hal-common/src/cpu_control/esp32s3.rs
@@ -33,7 +33,7 @@ pub struct CpuControl {
 }
 
 unsafe fn internal_park_core(core: Cpu) {
-    let rtc_control = crate::pac::RTC_CNTL::PTR;
+    let rtc_control = crate::peripherals::RTC_CNTL::PTR;
     let rtc_control = &*rtc_control;
 
     match core {
@@ -70,7 +70,7 @@ impl CpuControl {
 
     /// Unpark the given core
     pub fn unpark_core(&mut self, core: Cpu) {
-        let rtc_control = crate::pac::RTC_CNTL::PTR;
+        let rtc_control = crate::peripherals::RTC_CNTL::PTR;
         let rtc_control = unsafe { &*rtc_control };
 
         match core {
@@ -126,7 +126,7 @@ impl CpuControl {
         &mut self,
         entry: &mut (dyn FnMut() + Send),
     ) -> Result<AppCoreGuard, Error> {
-        let system_control = crate::pac::SYSTEM::PTR;
+        let system_control = crate::peripherals::SYSTEM::PTR;
         let system_control = unsafe { &*system_control };
 
         if !xtensa_lx::is_debugger_attached()