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enjoy-digital edited this page Nov 22, 2019
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Build your hardware, easily!
Copyright 2012-2019 / EnjoyDigital
LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.
LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.
+---------------+
|FPGA toolchains|
+----^-----+----+
| |
+--+-----v--+
+-------+ | |
| Migen +--------> |
+-------+ | | Your design
| LiteX +---> ready to be used!
| |
+----------------------+ | |
|LiteX Cores Ecosystem +--> |
+----------------------+ +-^-------^-+
(Eth, SATA, DRAM, USB, | |
PCIe, Video, etc...) + +
board target
file file
LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem:
Name | Build Status | Description |
---|---|---|
LiteDRAM | DRAM | |
LiteEth | Ethernet | |
LitePCIe | PCIe | |
LiteSATA | SATA | |
LiteSDCard | SD card | |
LiteICLink | Inter-Chip communication | |
LiteJESD204B | JESD204B | |
LiteVideo | VGA, DVI, HDMI | |
LiteScope | Logic analyzer |
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)