Home

                       __   _ __      _  __
                      / /  (_) /____ | |/_/
                     / /__/ / __/ -_)>  <
                    /____/_/\__/\__/_/|_|
                  Build your hardware, easily!

              Copyright 2012-2019 / EnjoyDigital

Welcome to LiteX wiki!

LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.

LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem.

Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.

Typical LiteX design flow:

                        +---------------+
                        |FPGA toolchains|
                        +----^-----+----+
                             |     |
                          +--+-----v--+
         +-------+        |           |
         | Migen +-------->           |
         +-------+        |           |        Your design
                          |   LiteX   +---> ready to be used!
                          |           |
+----------------------+  |           |
|LiteX Cores Ecosystem +-->           |
+----------------------+  +-^-------^-+
 (Eth, SATA, DRAM, USB,     |       |
  PCIe, Video, etc...)      +       +
                           board   target
                           file    file

LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem:

Name	Build Status	Description
LiteDRAM		DRAM
LiteEth		Ethernet
LitePCIe		PCIe
LiteSATA		SATA
LiteSDCard		SD card
LiteICLink		Inter-Chip communication
LiteJESD204B		JESD204B
LiteVideo		VGA, DVI, HDMI
LiteScope		Logic analyzer