-
Notifications
You must be signed in to change notification settings - Fork 581
Cores
Tim Ansell edited this page Apr 28, 2019
·
5 revisions
External LiteXXX cores
LiteDRAM | |
---|---|
Build Status | |
Description | Dynamic RAM controller |
Supported Standards | SDRAM, DDR, LPDDR, DDR2, DDR3, DDR4 |
Supported Hardware | Generic Verilog, Xilinx Spartan 6 + 7 Series + Ultrascale, Lattice ECP5 |
LiteEth | |
---|---|
Build Status | |
Description | Ethernet |
Supported Standards | 100, 1000 Mbit, MII, GMII & RGMII and many high speed tranceivers |
Supported Hardware | Generic Verilog, Xilinx Spartan 6 + 7 Series + Ultrascale, Lattice ECP5 |
LitePCIe | |
---|---|
Build Status | |
Description | PCIe |
Supported Standards | Gen1, Gen2, x1, x2 x4 |
Supported Hardware | Xilinx 7-series, Intel Cyclone V, and soon Lattice ECP5 |
LiteSATA | |
---|---|
Build Status | |
Description | SATA |
Supported Standards | 1.5/3.0/6.0 GBps |
Supported Hardware | Xilinx 7-series |
LiteUSB | |
---|---|
Build Status | |
Description | USB transfer |
Supported Standards | |
Supported Hardware |
LiteSDCard | |
---|---|
Build Status | |
Description | SD card |
Supported Standards | SD / SDHC / SDXC / SDUC, Default Speed, High Speed, UHS-I |
Supported Hardware | Xilinx Spartan 6 + 7 Series |
LiteICLink | |
---|---|
Build Status | |
Description | Inter-Chip communication |
Supported Standards | Custom protocol over Single Ended or LVDS Pair |
Supported Hardware | Xilinx 7-series + Ultrascale |
LiteJESD204B | |
---|---|
Build Status | |
Description | JESD204B |
Supported Standards | |
Supported Hardware | Xilinx 7-series + Ultrascale |
LiteVideo | |
---|---|
Build Status | |
Description | DVI, HDMI |
Supported Standards | |
Supported Hardware | Xilinx Spartan 6 + 7-series |
LiteScope | |
---|---|
Build Status | |
Description | Embedded FPGA logic analyzer |
Supported Standards | PCIe, UART, Ethernet |
Supported Hardware | Generic Verilog |
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)