litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk…

… only apply constraints on eth_rx_clk
enjoy-digital · Aug 31, 2023 · a071cc3 · a071cc3
1 parent 9854c9f
commit a071cc3
Showing 1 changed file with 10 additions and 4 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1702,8 +1702,11 @@ def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False,
             eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
             if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
                 self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
-                self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
-                self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
+                if not eth_rx_clk is eth_tx_clk:
+                    self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
+                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
+                else:
+                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
 
     # Add Etherbone --------------------------------------------------------------------------------
     def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
@@ -1761,8 +1764,11 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
             eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
             if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
                 self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
-                self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
-                self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
+                if not eth_rx_clk is eth_tx_clk:
+                    self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
+                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
+                else:
+                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
 
     # Add SPI Flash --------------------------------------------------------------------------------
     def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):