cores/vexriscv_smp add risc-v official debug support via --with-privi…

…leged-debug Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
enjoy-digital · Sep 8, 2023 · 112f78b · 112f78b
1 parent 022bdf3
commit 112f78b
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -47,6 +47,7 @@ class VexRiscvSMP(CPU):
     icache_width         = 32
     aes_instruction      = False
     out_of_order_decoder = True
+    privileged_debug     = False
     wishbone_memory      = False
     wishbone_force_32b   = False
     with_fpu             = False
@@ -71,6 +72,7 @@ def args_fill(parser):
         cpu_group.add_argument("--aes-instruction",              default=None,        help="Enable AES instruction acceleration.")
         cpu_group.add_argument("--without-out-of-order-decoder", action="store_true", help="Reduce area at cost of peripheral access speed")
         cpu_group.add_argument("--with-wishbone-memory",         action="store_true", help="Disable native LiteDRAM interface")
+        cpu_group.add_argument("--with-privileged-debug",        action="store_true", help="Enable official RISC-V debug spec")
         cpu_group.add_argument("--wishbone-force-32b",           action="store_true", help="Force the wishbone bus to be 32 bits")
         cpu_group.add_argument("--with-fpu",                     action="store_true", help="Enable the F32/F64 FPU")
         cpu_group.add_argument("--cpu-per-fpu",                  default="4",         help="Maximal ratio between CPU count and FPU count. Will instanciate as many FPU as necessary.")
@@ -99,6 +101,7 @@ def args_read(args):
         if(args.icache_ways):                  VexRiscvSMP.icache_ways           = int(args.icache_ways)
         if(args.aes_instruction):              VexRiscvSMP.aes_instruction       = bool(args.aes_instruction)
         if(args.without_out_of_order_decoder): VexRiscvSMP.out_of_order_decoder  = False
+        if(args.with_privileged_debug):        VexRiscvSMP.privileged_debug      = True
         if(args.with_wishbone_memory):         VexRiscvSMP.wishbone_memory       = True
         if(args.wishbone_force_32b):           VexRiscvSMP.wishbone_force_32b    = True
         if(args.with_fpu):
@@ -179,6 +182,7 @@ def generate_cluster_name():
         f"{'_Wm'   if VexRiscvSMP.wishbone_memory      else ''}" \
         f"{'_Wf32' if VexRiscvSMP.wishbone_force_32b   else ''}" \
         f"{'_Fpu' + str(VexRiscvSMP.cpu_per_fpu)  if VexRiscvSMP.with_fpu else ''}" \
+        f"{'_Pd'   if VexRiscvSMP.privileged_debug else ''}" \
         f"{'_Rvc'  if VexRiscvSMP.with_rvc else ''}"
 
     # Default Configs Generation.
@@ -264,6 +268,7 @@ def generate_netlist():
         gen_args.append(f"--litedram-width={VexRiscvSMP.litedram_width}")
         gen_args.append(f"--aes-instruction={VexRiscvSMP.aes_instruction}")
         gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}")
+        gen_args.append(f"--privileged-debug={VexRiscvSMP.privileged_debug}")
         gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
         if(VexRiscvSMP.wishbone_force_32b): gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}")
         gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}")