setup.py: Update for consistency with other setup.py scripts.

setup.py

@@ -4,20 +4,36 @@
 from setuptools import find_packages
 
 
+with open("README.md", "r", encoding="utf-8") as fp:
+    long_description = fp.read()
+
+
 setup(
-    name                 = "litescope",
-    description          = "Small footprint and configurable embedded FPGA logic analyzer core",
-    author               = "Florent Kermarrec",
-    author_email         = "[email protected]",
-    url                  = "http://enjoy-digital.fr",
-    download_url         = "https://github.com/enjoy-digital/litescope",
-    test_suite           = "test",
-    license              = "BSD",
-    python_requires      = "~=3.7",
-    packages             = find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
-    include_package_data = True,
-    keywords             = "HDL ASIC FPGA hardware design",
-    classifiers          = [
+    name                          = "litescope",
+    version                       = "2024.08",
+    description                   = "Small footprint and configurable embedded FPGA logic analyzer core",
+    long_description              = long_description,
+    long_description_content_type = "text/markdown",
+    author                        = "Florent Kermarrec",
+    author_email                  = "[email protected]",
+    url                           = "http://enjoy-digital.fr",
+    download_url                  = "https://github.com/enjoy-digital/litescope",
+    test_suite                    = "test",
+    license                       = "BSD",
+    python_requires               = "~=3.7",
+    install_requires              = ["pyyaml", "litex"],
+    extras_require                = {
+        "develop": [
+          "meson"
+          "pexpect"
+          "setuptools"
+          "requests"
+        ]
+    },
+    packages                      = find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
+    include_package_data          = True,
+    keywords                      = "HDL ASIC FPGA hardware design",
+    classifiers                   = [
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
         "Development Status :: 3 - Alpha",
@@ -26,7 +42,7 @@
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    entry_points={
+    entry_points         = {
         "console_scripts": [
             "litescope_cli=litescope.software.litescope_cli:main",
         ],