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4 changes: 2 additions & 2 deletions bittrue/models/python/en_cl_fix_pkg/en_cl_fix.py
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ def cl_fix_from_integer(a, r_fmt : FixFormat):
a = _clean_input(a)

if cl_fix_is_wide(r_fmt):
return a
return WideFix(a, r_fmt)
else:
return NarrowFix.from_integer(a, r_fmt)._data

Expand All @@ -165,7 +165,7 @@ def cl_fix_to_integer(a, a_fmt : FixFormat):
a = _clean_input(a)

if cl_fix_is_wide(a_fmt):
return a
return a.data
else:
return NarrowFix(a, a_fmt, copy=False).to_integer()

Expand Down
21 changes: 21 additions & 0 deletions en_cl_fix_dev.core
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
CAPI=2:

name : open-logic:open-logic-dev:en_cl_fix:2.3.1
description : local files (release plus WIP); see https://github.com/enclustra/en_cl_fix/blob/main/README.md

filesets:
rtl:
files:
- hdl/en_cl_fix_private_pkg.vhd
- hdl/en_cl_fix_saturate.vhd
- hdl/en_cl_fix_round.vhd
- hdl/en_cl_fix_resize.vhd
- hdl/en_cl_fix_pkg.vhd
file_type : vhdlSource-2008
logical_name : olo

targets:
default:
filesets :
- rtl

29 changes: 28 additions & 1 deletion hdl/en_cl_fix_pkg.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -595,7 +595,9 @@ package body en_cl_fix_pkg is

function cl_fix_shift_fmt(a_fmt : FixFormat_t; min_shift : integer; max_shift : integer) return FixFormat_t is
begin
-- synthesis translate_off
assert min_shift <= max_shift report "min_shift must be <= max_shift" severity Failure;
-- synthesis translate_on

return (a_fmt.S, a_fmt.I + max_shift, a_fmt.F - min_shift);
end;
Expand Down Expand Up @@ -733,8 +735,10 @@ package body en_cl_fix_pkg is
-- Parse Format
Index_v := Str'low;
Index_v := string_find_next_match(Str, '(', Index_v);
-- synthesis translate_off
assert Index_v > 0
report "cl_fix_format_from_string: Format string is missing '('" severity Failure;
-- synthesis translate_on
-- Number of sign bits must be 0 or 1
if Str(Index_v+1) = '0' then
Format_v.S := 0;
Expand All @@ -744,16 +748,22 @@ package body en_cl_fix_pkg is
report "cl_fix_format_from_string: Unsupported number of sign bits: " & Str(Index_v+1) severity Failure;
end if;
Index_v := string_find_next_match(Str, ',', Index_v+1);
-- synthesis translate_off
assert Index_v > 0
report "cl_fix_format_from_string: Format string is missing ',' between S and I" severity Failure;
-- synthesis translate_on
Format_v.I := string_parse_int(Str, Index_v+1);
Index_v := string_find_next_match(Str, ',', Index_v+1);
-- synthesis translate_off
assert Index_v > 0
report "cl_fix_format_from_string: Format string is missing ',' between I and F" severity Failure;
-- synthesis translate_on
Format_v.F := string_parse_int(Str, Index_v+1);
Index_v := string_find_next_match(Str, ')', Index_v+1);
-- synthesis translate_off
assert Index_v > 0
report "cl_fix_format_from_string: Format string is missing ')'" severity Failure;
-- synthesis translate_on
return Format_v;
end;

Expand Down Expand Up @@ -809,13 +819,16 @@ package body en_cl_fix_pkg is
constant ChunkCount_c : positive := (cl_fix_width(result_fmt) + ChunkSize_c - 1)/ChunkSize_c;
variable ASat_v : real;
variable Chunk_v : std_logic_vector(ChunkSize_c-1 downto 0);
variable ChunkInt_v : integer;
variable Result_v : std_logic_vector(ChunkSize_c*ChunkCount_c-1 downto 0);
begin
-- Saturation is mandatory in this function (because wrapping has not been implemented)
-- synthesis translate_off
assert saturate = SatWarn_s or saturate = Sat_s
report "cl_fix_for_real: Saturation mode must be SatWarn_s or Sat_s"
severity Failure;

-- synthesis translate_on

-- Saturate
if a > max_real(result_fmt) then
ASat_v := max_real(result_fmt);
Expand Down Expand Up @@ -937,8 +950,10 @@ package body en_cl_fix_pkg is
begin
-- Allow the designer to ignore the worst-case result format (with caution).
if fmt_check then
-- synthesis translate_off
assert result_fmt = cl_fix_round_fmt(a_fmt, result_fmt.F, round)
report "cl_fix_round: Invalid result format. Use cl_fix_round_fmt()." severity Failure;
-- synthesis translate_on
end if;

-- Write the input value into mid_v with correct binary point alignment.
Expand Down Expand Up @@ -983,12 +998,16 @@ package body en_cl_fix_pkg is
) return std_logic_vector is
variable result_v : std_logic_vector(cl_fix_width(result_fmt)-1 downto 0);
begin
-- synthesis translate_off
assert result_fmt.F = a_fmt.F report "cl_fix_saturate: Number of frac bits cannot change." severity Failure;
-- synthesis translate_on

-- Saturation warning
if saturate = Warn_s or saturate = SatWarn_s then
-- synthesis translate_off
assert cl_fix_in_range(a, a_fmt, result_fmt)
report "cl_fix_saturate : Saturation warning!" severity Warning;
-- synthesis translate_on
end if;

-- Write the input value into result_v with correct binary point alignment.
Expand Down Expand Up @@ -1047,8 +1066,10 @@ package body en_cl_fix_pkg is
begin
-- Allow the designer to ignore the worst-case result format (with caution).
if fmt_check then
-- synthesis translate_off
assert result_fmt = cl_fix_round_fmt(a_fmt, result_fmt.F, round)
report "cl_fix_recommended_pipelining: Invalid result format. Use cl_fix_round_fmt()." severity Failure;
-- synthesis translate_on
end if;

-- Registering is not needed if zero logic is used. This happens in two cases:
Expand All @@ -1057,9 +1078,11 @@ package body en_cl_fix_pkg is
return 0;
else
-- If a new rounding mode is defined, then appropriate behavior must be implemented.
-- synthesis translate_off
assert round = NonSymPos_s or round = NonSymNeg_s or round = SymInf_s or round = SymZero_s or round = ConvEven_s or round = ConvOdd_s
report "cl_fix_recommended_pipelining: Unhandled rounding mode."
severity Failure;
-- synthesis translate_on
end if;
-- (2) If the number of fractional bits isn't being decreased.
if result_fmt.F >= a_fmt.F then
Expand All @@ -1074,19 +1097,23 @@ package body en_cl_fix_pkg is
saturate : FixSaturate_t
) return natural is
begin
-- synthesis translate_off
assert result_fmt.F = a_fmt.F
report "cl_fix_recommended_pipelining: Number of frac bits cannot change during saturation."
severity Failure;
-- synthesis translate_on

-- Registering is not needed if zero logic is used. This happens in two cases:
-- (1) During wrapping.
if saturate = None_s or saturate = Warn_s then
return 0;
else
-- If a new saturation mode is defined, then appropriate behavior must be implemented.
-- synthesis translate_off
assert saturate = Sat_s or saturate = SatWarn_s
report "cl_fix_recommended_pipelining: Unhandled saturation mode."
severity Failure;
-- synthesis translate_on
end if;
-- (2) If the number of integer bits is not being decreased, and the number of sign bits is
-- not being changed.
Expand Down
4 changes: 4 additions & 0 deletions hdl/en_cl_fix_private_pkg.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,9 @@ package body en_cl_fix_private_pkg is
variable MatchIdx_v : integer := -1;
begin
-- Checks
-- synthesis translate_off
assert StartIdx <= Str'high and StartIdx >= Str'low report "string_find_next_match: StartIdx out of range" severity Failure;
-- synthesis translate_on

-- Implementation
while (not Match_v) and (CurrentIdx_v <= Str'high) loop
Expand Down Expand Up @@ -203,7 +205,9 @@ package body en_cl_fix_private_pkg is
variable AbsoluteVal_v : integer := 0;
begin
-- Checks
-- synthesis translate_off
assert StartIdx <= Str'high and StartIdx >= Str'low report "string_parse_int: StartIdx out of range" severity Failure;
-- synthesis translate_on

-- Remove leading spaces
while Str(CurrentIdx_v) = ' ' loop
Expand Down