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docker_opts = --rm -v /$(shell pwd)://work -w //work --user $(shell id -u) | ||
docker_img ?= ghdl/vunit:gcc | ||
test_threads = 4 | ||
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default: run | ||
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run: | ||
docker run ${docker_opts} ${docker_img} sh -c 'python3 run.py -p ${test_threads}' |
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from os.path import join, dirname | ||
from vunit import VUnit | ||
from subprocess import check_call | ||
import os | ||
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ui = VUnit.from_argv() | ||
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ui.add_osvvm() | ||
ui.add_verification_components() | ||
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ui.add_source_files_from_csv(join(dirname(__file__), "vunit_files.csv")) | ||
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lib = ui.library("lib") | ||
lib.set_sim_option("enable_coverage", True) | ||
lib.set_compile_option("ghdl.flags", ["-g", "-O2", "-Wc,-fprofile-arcs", "-Wc,-ftest-coverage"]) | ||
lib.set_sim_option("ghdl.elab_flags", ["-Wl,-lgcov", "-Wl,--coverage"]) | ||
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def post_run(results): | ||
#srcs = join(dirname(__file__), "src/rtl/*.vhd").lstrip("/") | ||
#check_call(["gcovr", "-r", os.getcwd(), "-f", srcs]) | ||
check_call(["gcovr", "-r", os.getcwd()]) | ||
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ui.main(post_run=post_run) |
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity serial_io is | ||
port( | ||
-- generic signals | ||
clk : in std_logic; | ||
rst : in std_logic; | ||
-- input data | ||
io_i : in std_logic; | ||
-- output-data | ||
io_o : out std_logic | ||
); | ||
end serial_io; | ||
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architecture Behavioral of serial_io is | ||
signal r : std_logic; | ||
begin | ||
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proc : process(clk, rst) is | ||
begin | ||
if rst = '1' then | ||
r <= '1'; | ||
io_o <= '1'; | ||
elsif rising_edge(clk) then | ||
r <= io_i; | ||
io_o <= r; | ||
end if; | ||
end process proc; | ||
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end Behavioral; |
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library IEEE; | ||
use IEEE.STD_LOGIC_1164.all; | ||
use IEEE.NUMERIC_STD.all; | ||
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library vunit_lib; | ||
context vunit_lib.vunit_context; | ||
context vunit_lib.vc_context; | ||
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library osvvm; | ||
use osvvm.RandomPkg.all; | ||
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entity tb_serial_io is | ||
generic( | ||
runner_cfg : string); | ||
end entity; | ||
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architecture tb of tb_serial_io is | ||
constant clk_period : time := 1 sec / (1000 * 1000); | ||
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signal rst : std_logic := '1'; | ||
signal clk : std_logic := '0'; | ||
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shared variable rnd_stimuli, rnd_expected : RandomPType; | ||
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constant uart_slv_bfm : uart_slave_t := new_uart_slave(initial_baud_rate => 57600, | ||
data_length => 8); | ||
constant uart_slv : stream_slave_t := as_stream(uart_slv_bfm); | ||
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constant uart_ma_bfm : uart_master_t := new_uart_master(initial_baud_rate => 57600); | ||
constant uart_ma : stream_master_t := as_stream(uart_ma_bfm); | ||
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signal io_i, io_o : std_logic; | ||
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begin | ||
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main : process | ||
variable rnd8 : std_logic_vector(7 downto 0); | ||
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begin | ||
test_runner_setup(runner, runner_cfg); | ||
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wait until rising_edge(clk); | ||
wait until rising_edge(clk); | ||
wait until rising_edge(clk); | ||
rst <= '0'; | ||
wait until rising_edge(clk); | ||
wait until rising_edge(clk); | ||
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-- Initialize to same seed to get same sequence | ||
rnd_stimuli.InitSeed(rnd_stimuli'instance_name); | ||
rnd_expected.InitSeed(rnd_stimuli'instance_name); | ||
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while test_suite loop | ||
if run("test_send_one_byte") then | ||
rnd8 := rnd_stimuli.RandSlv(8); | ||
push_stream(net, uart_ma, rnd8); | ||
check_stream(net, uart_slv, rnd8(7 downto 0)); | ||
end if; | ||
end loop; | ||
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test_runner_cleanup(runner); | ||
wait; | ||
end process; | ||
test_runner_watchdog(runner, 10 ms); | ||
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clk <= not clk after (clk_period / 2); | ||
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dut : entity work.serial_io | ||
port map( | ||
clk => clk, | ||
rst => rst, | ||
io_i => io_i, | ||
io_o => io_o | ||
); | ||
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uart_master_bfm : entity vunit_lib.uart_master | ||
generic map( | ||
uart => uart_ma_bfm) | ||
port map( | ||
tx => io_i); | ||
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uart_slave_bfm : entity vunit_lib.uart_slave | ||
generic map( | ||
uart => uart_slv_bfm) | ||
port map( | ||
rx => io_o); | ||
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end architecture; |
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#!/usr/bin/env sh | ||
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set -e | ||
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IMG=ghdl/vunit:gcc | ||
docker pull "$IMG" | ||
time make docker_img="$IMG" | ||
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rm -rf vunit_out *.gc* | ||
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IMG=ghdl/vunit:gcc-master | ||
docker pull "$IMG" | ||
time make docker_img="$IMG" | ||
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rm -rf vunit_out *.gc* |
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lib,src/rtl/serial_io.vhd | ||
lib,src/sim/tb_serial_io.vhd |