Improve DeepSeek-V4-Flash throughput on MI300X

[fergusfinn]

Summary

Improves DeepSeek-V4-Flash serving throughput on MI300X on top of #11.

This PR reduces overhead in the sparse MLA decode path and MXFP4 MoE path while keeping the serving behavior introduced by the MI300X bring-up PR.

What Changed

• Makes sparse MLA decode metadata reusable under graph replay.
• Writes sparse MLA decode results directly into the caller output buffer.
• Caches the bf16 projection weight used by the sparse MLA path.
• Selects faster sparse MLA decode launch shapes for MI300X serving.
• Applies MI300X-specific MXFP4 OGS tuning for the DeepSeek-V4-Flash routed expert path.
• Removes profiling-only hooks and attribution-only gates from the final code.

Performance

On the 512 input / 512 output benchmark, the tuned path reaches 2699 output tok/s per GPU on 2x MI300X, up from 2485 output tok/s per GPU after bring-up.

Test Plan

• 512 input / 512 output end-to-end throughput benchmark on DeepSeek-V4-Flash.
• Python compile check for the modified ROCm and MoE modules.
• Compare generated-output behavior against the bring-up baseline.
• Check both ramp and sustained serving shapes for regressions.

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[chatgpt-codex-connector]

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[chatgpt-codex-connector]

Keep SWA ragged metadata on the static path

When DSV4_STATIC_DECODE_RAGGED_METADATA_DEFAULT is unset, this False default sends every SWA decode batch through build_ragged_indices_from_dense, even though _forward_decode always passes swa_metadata.decode_swa_ragged_* as the main sparse indices. That reintroduces a per-step dynamic allocation and the int(indptr[-1].item()) host sync that build_ragged_indices_from_dense_out was added to avoid, so the default decode path loses the static-metadata behavior for the SWA portion while the top-k portion still gets it.

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[doubleword-code]

Summary

This PR enables ROCm-specific throughput optimizations for DeepSeek V4 inference, primarily focused on:

1. ROCm Triton kernels for fused Q-normalization + RoPE + KV cache insertion operations
2. FP8 FNUZ format support for ROCm platforms (MI300X/gfx942)
3. Dynamic tile tuning for MoE OGS (Operator Graph Schedule) optimized for DeepSeek V4 Flash MXFP4 shapes
4. Sparse attention improvements including ragged index support and memory metrics logging
5. Comprehensive test coverage for cache layout correctness and fused kernel parity

The changes are well-structured with appropriate platform guards (current_platform.is_rocm()) and environment-variable-based configuration for experimental features. The test coverage is thorough, particularly for the new fused KV cache operations.

Verdict: Needs minor changes before approval — see blocking finding below regarding an unguarded import that could cause failures on systems without triton_kernels installed.

Research notes

• FP8 formats: ROCm uses FNUZ (float8_e4m3fnuz / tl.float8e4b8) while CUDA uses FP8 E4M3 (float8_e4m3fn / tl.float8e4nv). The PR correctly handles both via current_platform.is_fp8_fnuz() checks.
• UE8M0 quantization: The scale encoding (exponent + 127) matches the DeepSeek V4 specification for power-of-2 scales stored as uint8 exponents.
• FlashMLA sparse backend: The 576-byte alignment requirement for KV cache blocks is correctly maintained throughout the changes.

Suggested next steps

1. Blocker: Guard the _ogs_opt_flags import to prevent failures when triton_kernels is unavailable
2. Document the intentional asymmetry in DSV4_STATIC_DECODE_RAGGED_METADATA_DEFAULT defaults (True for C128A, False for SWA)
3. Consider enabling DSV4_AITER_PREFILL_MQA_LOGITS_MAX_N with a sensible non-zero default once LDS constraints are resolved

General findings

Code quality observations

• The new Triton kernels follow vLLM's existing patterns for platform-specific implementations
• Environment variable naming convention (DSV4_*, VLLM_ROCM_*) is consistent
• Memory workspace management correctly uses the simultaneous workspace pattern for prefill chunking
• The shape dump utilities (_maybe_dump_dsv4_moe_shape, _maybe_dump_sparse_decode_shape) are properly guarded against graph capture

Test coverage

• New test file test_deepseek_v4_cache_layout_correctness.py provides excellent byte-level verification of cache layouts
• test_fused_deepseek_v4_qnorm_rope_kv_insert.py thoroughly validates the fused kernel against reference implementations
• Existing tests in test_rocm_triton_attn_dsv4.py have been extended to cover ragged index operations

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py:374 — Unguarded import of triton_kernels submodule
  • (demoted: line 374 (side=RIGHT) is not part of any diff hunk in vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py)
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:662 — AITER fast path disabled by default
  • (demoted: line 662 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Nit vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse_dsv4.py:397 — Asymmetric environment variable defaults for C128A vs SWA paths
  • (demoted: path "vllm/v1/attention/backends/mla/rocm_aiter_mla_sparse_dsv4.py" is not in the PR diff)
• Non-blocking vllm/v1/attention/ops/deepseek_v4_ops/cache_utils.py:179 — FP8_MAX constant fix - good catch
  • (demoted: path "vllm/v1/attention/ops/deepseek_v4_ops/cache_utils.py" is not in the PR diff)

[doubleword-code]

Summary

This PR introduces throughput optimizations for DeepSeek-V4 on AMD ROCm platforms, including FP8 FNUZ support, dynamic kernel configuration tuning, vectorized attention kernels, and sparse attention chunking. The changes are well-structured with corresponding test updates. However, there is one correctness issue in the vectorized paged MQA logits implementation that needs fixing.

Verdict: Needs changes before merging.

Research Notes

• FP8 E8M0 encoding: The w8a8_utils.py change correctly handles E8M0 scale doubling by incrementing the uint8 exponent (+1) rather than multiplying by 2.0, since scale = 2^(exp-bias).
• Triton FP8 types: tl.float8e4b8 (FNUZ, bias=8) for AMD gfx950 vs tl.float8e4nv (standard, bias=15) for NVIDIA - the conditional based on is_fp8_fnuz() is correct.
• AMD ROCm FP8 dtype: current_platform.fp8_dtype() dynamically returns the appropriate torch dtype.

Suggested Next Steps

1. Fix the vectorized fp8_paged_mqa_logits_torch for next_n==1 - the einsum broadcasting across batch dimensions combined with late masking may cause numerical issues with garbage values in padded positions.
2. Add explicit test coverage for batch_size > 1 in the vectorized path.
3. Consider documenting the new DSV4_* and VLLM_ROCM_DSV4_* environment variables.

General Findings

• Correctness: The FP8 type handling for FNUZ is correct. The weight caching logic properly invalidates on tensor reallocation.
• Performance: The OGS tile tuning for DeepSeek-V4-Flash on MI300X is well-motivated with measured improvements cited in commit messages.
• Testing: New parametrized tests for sparse attention kernels improve coverage.
• Code Quality: Environment variable naming could be standardized; some new functions lack docstrings.

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:417 — The einsum here computes per-batch attention correctly, but the subsequent masking at line 422-424 happens after computing scores for ALL positions up to max_model_len. For positions beyond context_len[i], the cache_value contains garbage data from unrelated physical blocks (due to clamping block indices to 0 at line 408). While masked out in the final result, intermediate operations (ReLU at line 418, scale multiplication at line 419) on these garbage values could propagate NaN/Inf in edge cases.
  • (demoted: line 417 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:622 — The hard-coded value 128 assumes each scale entry applies to exactly 128 tokens. This matches the indexer path quantization block size, but if this function is ever called with scales from a different quantization scheme (e.g., the attention path with block_size=64), the dequantization would be incorrect.
  • (demoted: line 622 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Nit vllm/model_executor/layers/quantization/utils/w8a8_utils.py:128 — The E8M0 scale doubling logic (+1 to uint8 exponent) is correct, but consider adding a comment explaining why this differs from the standard * 2.0 operation. For example:
  • (demoted: path "vllm/model_executor/layers/quantization/utils/w8a8_utils.py" is not in the PR diff)
• Nit vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:106 — Missing docstring. This function determines Triton kernel launch parameters (block_h, block_k, num_warps) based on query count and head_dim. A brief docstring explaining the decision tree and the role of environment variable overrides would improve maintainability.
  • (demoted: code self-check failed at vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:106: diff has num_queries: int,, model claimed def _select_sparse_decode_config()
• Nit vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:688 — Consider consolidating environment variable documentation. This PR introduces many DSV4_* and VLLM_ROCM_DSV4_* variables across multiple files. A central location (e.g., a config module or documentation file) listing all variables with their defaults and purposes would help operators tune performance.
  • (demoted: line 688 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)

[doubleword-code]

Summary

This PR delivers substantial throughput improvements for DeepSeek V4 on ROCm/MI300X through multiple optimizations: dynamic sparse MLA decode launch (+34.16 tok/s), MXFP4 OGS tile tuning (+106.80 tok/s), bf16 projection weight caching, and direct output buffer reuse. The changes span 18 files with careful attention to platform-specific FP8 formats (FNUZ vs standard) and CUDA graph capture safety.

Verdict: Needs changes before merge - one blocking correctness issue regarding Triton FP8 type consistency, plus several non-blocking improvements for robustness.

Research notes

• Triton FP8 types: According to Triton's type system, tl.float8e4b8 corresponds to float8_e4m3fnuz (AMD FNUZ format used on MI300X/gfx942), while tl.float8e4nv is standard float8_e4m3fn (NVIDIA). The type tl.float8e4b15 represents a different variant (float8_e4m3b15). See Triton documentation.

• ROCm FP8 FNUZ: AMD MI300X (gfx942) uses FNUZ format where float8_e4m3fnuz has max value 224.0 vs 448.0 for standard FP8. The code correctly uses torch.finfo(current_platform.fp8_dtype()).max to handle both platforms.

• E8M0 scale adjustment: For float8_e8m0fnu, incrementing the uint8 representation by 1 is mathematically equivalent to multiplying by 2.0 (since exponent bias is 127). The w8a8_utils.py change is correct.

Suggested next steps

1. BLOCKING: Investigate and fix the inconsistent Triton FP8 type usage (tl.float8e4b8 vs tl.float8e4b15) across the codebase
2. NON-BLOCKING: Add graph-capture guard to rocm_inv_rope_einsum weight caching to prevent potential issues during model warmup
3. NON-BLOCKING: Improve assertion messages in metadata builders to aid debugging
4. NON-BLOCKING: Consider documenting environment variable semantics more clearly

General findings

Correctness & Safety

• The FNUZ handling via current_platform.is_fp8_fnuz() is consistently applied across cache_utils.py, fused_compress_quant_cache.py, compressor.py, and rocm_aiter_mla_sparse.py
• Graph capture safety checks are present in shape dump functions and MoE shape collection
• The full-window optimization (max_seq_len <= topk_tokens) correctly bypasses logits computation when all tokens fit in top-k

Testing

• New test file test_deepseek_v4_cache_layout_correctness.py provides byte-level validation of KV cache layout
• Existing tests updated to use platform-aware current_platform.fp8_dtype() instead of hardcoded types
• Test coverage appears adequate for the core quantize/dequantize paths

Performance Optimizations

• Direct output buffer passing avoids unnecessary copies when dtype matches (controlled by DSV4_SPARSE_ATTN_DECODE_DIRECT_OUT_DEFAULT)
• Static bf16 weight caching in rocm_inv_rope_einsum reduces redundant dequantization
• Dynamic block_h/block_k selection based on query count and extra indices improves occupancy

---

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1798 — Inconsistent Triton FP8 type usage across the codebase.
  • (demoted: line 1798 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1298 — Weight caching in rocm_inv_rope_einsum lacks graph-capture guard.
  • (demoted: line 1298 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Non-blocking vllm/v1/attention/backends/mla/sparse_swa.py:410 — Assertion lacks context for debugging.
  • (demoted: path "vllm/v1/attention/backends/mla/sparse_swa.py" is not in the PR diff)
• Nit vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:122 — Environment variable naming is slightly confusing.
  • (demoted: line 122 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Nit vllm/model_executor/layers/quantization/utils/w8a8_utils.py:128 — Consider adding comment explaining E8M0 scale adjustment.
  • (demoted: path "vllm/model_executor/layers/quantization/utils/w8a8_utils.py" is not in the PR diff)
• Nit vllm/models/deepseek_v4/common/ops/cache_utils.py:199 — Consider verifying is_fp8_fnuz() behavior during initialization.
  • (demoted: path "vllm/models/deepseek_v4/common/ops/cache_utils.py" is not in the PR diff)

[doubleword-code]

Summary

This PR removes DSV4 profiling/attribution-only controls and bakes in measured throughput optimizations for DeepSeek-V4 on MI300X (ROCm). The six-step attribution shows cumulative gains of ~160 output tok/s from MLA decode metadata, direct output, bf16 weight cache, dynamic launch, and MXFP4 OGS tile tuning.

The changes are well-structured and the performance claims are backed by fixed benchmark numbers. However, there is one significant issue that needs addressing before merge.

Verdict: Needs changes — see blocking finding below.

Research notes

• Reviewed Triton kernel launch parameter selection patterns in similar ROCm attention code; the _select_sparse_decode_config heuristic follows expected CDNA3 tuning practices (block_h/block_k tradeoffs based on query batch size).
• Checked OWASP guidance for input handling — no user-controlled inputs flow into the changed paths without validation.
• The build_ragged_indices_from_dense_out function's docstring explicitly states it is the "CUDA-graph-friendly decode variant" that avoids host sync from int(indptr[-1].item()). The regression to build_ragged_indices_from_dense in the SWA path contradicts this design intent.

Suggested next steps

1. Fix the unused buffer allocation in DeepseekV4ROCMAiterSparseSWAMetadataBuilder (blocking)
2. Consider adding brief comments documenting the heuristic thresholds in _select_sparse_decode_config
3. Verify thread-safety assumptions for the global _ogs_opt_flags mutation if concurrent inference is supported

General findings

• The removal of debug logging (_log_sparse_prefill_mem_metrics) is appropriate for production code.
• The max_seq_len fast-path optimization for full-window topk is sound and correctly falls back when the field is absent.
• The output-buffer passing pattern in attention functions (out parameter) is correctly implemented for CUDA graph capture.

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/models/deepseek_v4/amd/rocm.py:535 — Pre-allocated buffers are ignored here, causing unnecessary tensor allocations in the decode loop.
  • (demoted: code self-check failed at vllm/models/deepseek_v4/amd/rocm.py:535: diff has return DeepseekV4ROCMAiterSparseSWAMetadata(, model claimed ragged_indices, ragged_indptr = build_ragged_indices_from_dense()
• Nit vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:37 — The heuristic thresholds (80, 256, 32 queries; extra_per_query <= 8 boundary) lack documentation explaining their origin.
  • (demoted: code self-check failed at vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:37: diff has ), model claimed def _select_sparse_decode_config()

[doubleword-code]

Non-blocking: This context manager modifies global module state (_ogs_opt_flags), which could cause issues under concurrent inference requests.

Why it matters: If multiple threads invoke MoE forward passes simultaneously with different shape constraints, the constraint mutations could race. PyTorch inference is typically single-threaded per model, but multi-model serving or data-parallel scenarios could expose this.

Suggested fix: Consider whether the constraints can be passed directly to matmul_ogs via its API rather than mutating global state, or document the threading assumptions. If concurrent inference is not supported, add a comment stating this explicitly.

[doubleword-code]

Summary

This PR introduces performance optimizations for DeepSeek V4 throughput replay on ROCm, including:

• EAGLE3 spec decode enhancements with fc_norm and norm_output configuration options
• Fused GPU kernel for mamba state postprocessing (eliminating CPU-GPU sync)
• Various MLA decode optimizations

The changes are substantial and well-tested overall, but I've identified one blocking issue related to weight loading for the new fc_norm feature, and one non-blocking issue regarding a potential edge case in the Triton kernel.

Verdict: Needs changes before merge due to missing weight loading logic for fc_norm.

Research notes

• Reviewed Triton kernel documentation for pointer arithmetic and bounds checking
• Cross-referenced mamba state handling patterns in existing codebase (vllm/v1/worker/mamba_utils.py)
• Examined weight loading patterns in other model files using AutoWeightsLoader
• Verified speculative decoding token counting logic in scheduler output

Suggested next steps

1. Blocking: Add skip logic for fc_norm weights in load_weights() method (see inline comment)
2. Non-blocking: Consider adding guard for dest_block_idx < 0 in Triton kernel as defensive programming
3. Optional: Add test coverage for edge case where num_tokens_running_state = 0

General findings

Architecture observations

• The fused GPU kernel (postprocess_mamba_fused_kernel) is well-designed and eliminates a significant CPU-GPU synchronization bottleneck
• The MambaBuffers abstraction cleanly separates preprocess vs postprocess concerns
• Test coverage for the fused kernel is comprehensive (19 test methods in test_mamba_utils.py)

Code quality

• Good use of type hints and docstrings throughout
• The Triton kernel includes detailed comments explaining memory layout decisions
• Some complexity in gpu_model_runner.py around is_token_ids handling could benefit from additional comments

---

Note: The removed code at line 1756-1757 in gpu_model_runner.py (if self.enable_prompt_embeds: self.is_token_ids.gpu[:num_common_tokens] = True) appears intentional since sampled tokens from previous iterations are always token IDs (not embeddings). However, this assumption should be verified if prompt embeds can ever interleave with decode tokens.

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/model_executor/models/llama_eagle3.py:209 — Missing weight skip logic for fc_norm in load_weights() method.
  • (demoted: path "vllm/model_executor/models/llama_eagle3.py" is not in the PR diff)
• Non-blocking vllm/v1/worker/mamba_utils.py:93 — Potential negative dest_block_idx when aligned_new_computed < block_size.
  • (demoted: path "vllm/v1/worker/mamba_utils.py" is not in the PR diff)
• Non-blocking vllm/v1/worker/gpu_model_runner.py:1779 — is_token_ids not explicitly set in common-case optimization path when enable_prompt_embeds=True.
  • (demoted: path "vllm/v1/worker/gpu_model_runner.py" is not in the PR diff)

[doubleword-code]

Summary

This PR delivers DeepSeek V4 bringup on AMD MI300X through a methodical six-step throughput attribution approach, with each optimization measured against a fixed benchmark. The changes span Triton kernels, cache management, metadata handling, and MoE routing logic.

Verdict: Needs changes before merge due to one potential issue with scale handling and some missing edge case coverage.

Research notes

• ONNX Float8 spec: Documents E4M3FNUZ (exponent bias 8) vs E4M3FN (bias 7) formats. Confirms the fix from float8e4b15 to float8e4b8 is correct for MI300X FNUZ.
• AMD ROCm FP8: MI300X (gfx942) uses FNUZ format (torch.float8_e4m3fnuz), while newer GPUs use non-FNUZ.

Key findings

Correctness fixes (good)

1. FP8 type correction: The change from tl.float8e4b15 to tl.float8e4b8 for FNUZ fixes a real bug - E4M3FNUZ has exponent bias 8, not 15.

2. MoE expert_map fix (vllm/model_executor/layers/fused_moe/layer.py:1320): Correctly returns canonical _expert_map for non-AITER MXFP4 backends instead of incorrectly using expert_mask just because ROCm AITER is globally enabled.

3. EMULATION backend support (vllm/model_executor/layers/fused_moe/oracle/mxfp4.py:1481): Adds missing handler for the EMULATION backend in weight conversion.

Potential issues

1. Scale handling in fp8_mqa_logits_torch (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:521): The defensive else branch with repeat_interleave(128) doesn't match any known scale format in the codebase. Current allocation pattern produces [N, 4] uint8 → [N, 1] float32, so this path shouldn't trigger, but the logic appears incorrect for block-scale scenarios.

2. Weight cache key invalidation (vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1120): Cache stored on module attrs could persist across different shape configurations if n_local_groups or o_lora_rank change.

General findings (auto-demoted from inline due to pre-validation)

• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:521 — Scale handling logic here appears defensive but the else branch doesn't match observed allocation patterns.
  • (demoted: line 521 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1120 — Weight caching stores dequantized bf16 weights on module attributes with cache key invalidation.
  • (demoted: code self-check failed at vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1120: diff has n_local_groups,, model claimed wo_a._vllm_rocm_bf16_weight_cache = wo_a_weight)
• Non-blocking vllm/v1/attention/backends/mla/sparse_swa.py:409 — Assertion assumes common_attn_metadata.seq_lens_cpu_upper_bound is always populated when num_prefills > 0.
  • (demoted: path "vllm/v1/attention/backends/mla/sparse_swa.py" is not in the PR diff)
• Blocking vllm/model_executor/layers/fused_moe/layer.py:1320 — CRITICAL BUGFIX - This correctly fixes expert routing for non-AITER MXFP4 backends on ROCm.
  • (demoted: path "vllm/model_executor/layers/fused_moe/layer.py" is not in the PR diff)
• Blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1507 — CRITICAL BUGFIX - Corrects FP8 type for FNUZ format on MI300X.
  • (demoted: line 1507 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Blocking vllm/model_executor/layers/quantization/utils/w8a8_utils.py:128 — CORRECT - Properly handles FNUZ scale adjustment.
  • (demoted: path "vllm/model_executor/layers/quantization/utils/w8a8_utils.py" is not in the PR diff)

[doubleword-code]

Summary

This PR brings up DeepSeek V4 on MI300X (gfx942) with a six-step throughput attribution stack, enabling MLA sparse attention, MXFP4 MoE optimizations, and HIP-graph-safe paths. The changes are substantial (~1.1k net lines added) and touch performance-critical kernels across ROCm attention, MoE, and cache handling.

Verdict: Needs changes before merge. There is one correctness issue in the OGS constraints context manager that could cause suboptimal or conflicting tile configurations, plus several non-blocking items around safety checks and documentation.

Research notes

• Fetched OWASP guidance on input validation and type safety for GPU kernels - confirms the need for explicit bounds checks even when masking appears sufficient.
• Reviewed Triton documentation on tl.float8e4b8 (FNUZ) vs tl.float8e4nv - the conditional usage throughout the PR is correct.
• Checked ONNX float8 spec for e4m3fn→e4m3fnuz conversion - the scale doubling logic in w8a8_utils.py matches the standard.
• Examined similar patterns in PyTorch's torch.autograd.profiler context managers - confirmed that saving/restoring state should not re-apply previous constraints during the nested yield.

Suggested next steps

1. Fix _temporary_ogs_constraints context manager (Blocking) - Remove the line that restores previous constraints inside the try block; only apply the new constraints parameter during the yield.
2. Add runtime assertion for indptr_out[0] == 0 in build_ragged_indices_from_dense_out (Non-blocking).
3. Restore bounds check in fp8_paged_mqa_logits_torch or document why it's safe without (Non-blocking).
4. Add test coverage for nested OGS constraint calls to verify isolation semantics (Non-blocking).

General findings

• The FP8 FNUZ dialect handling is thorough and consistent across all affected kernels (compressor, cache utils, attention ops).
• The workspace sizing logic in the dynamic prefill path correctly accounts for compressed vs uncompressed token counts.
• Test coverage additions are appropriate, particularly the cache layout correctness tests and parameterized ragged kernel tests.
• The expert_map fix for non-AITER MXFP4 backend correctly addresses the routing bug described in commit 8b5f7aa.

General findings (auto-demoted from inline due to pre-validation)

• Blocking vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py:85 — This line restores the previous constraints before applying the new ones, causing both sets to be active simultaneously during the yield.
  • (demoted: code self-check failed at vllm/model_executor/layers/fused_moe/experts/gpt_oss_triton_kernels_moe.py:85: diff has if previous:, model claimed _ogs_opt_flags.update_opt_flags_constraints(previous))
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:1268 — This function relies on the caller initializing indptr_out[0] to zero, but there's no runtime assertion to catch violations.
  • (demoted: line 1268 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Non-blocking vllm/v1/attention/ops/rocm_aiter_mla_sparse.py:323 — The original paged MQA logits code had assert seq_len <= max_model_len to catch invalid context lengths. This vectorized refactoring removed that check.
  • (demoted: line 323 (side=RIGHT) is not part of any diff hunk in vllm/v1/attention/ops/rocm_aiter_mla_sparse.py)
• Nit vllm/models/deepseek_v4/amd/rocm.py:764 — The dynamic_workspace = True assignment on line 754 followed by an immediate if dynamic_workspace: block suggests this flag was intended for future A/B comparison but is now dead code.
  • (demoted: line 764 (side=RIGHT) is not part of any diff hunk in vllm/models/deepseek_v4/amd/rocm.py)