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ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238

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merged 7 commits into from
Jan 23, 2024
Merged

ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238

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30f0bfa
Implement IF_SVE_ED_1A, IF_SVE_EE_1A
amanasifkhalid Jan 19, 2024
57d1e2c
Implement IF_SVE_EB_1A
amanasifkhalid Jan 19, 2024
ef49578
Implement IF_SVE_EC_1A
amanasifkhalid Jan 19, 2024
e17493e
Fix PerfScore
amanasifkhalid Jan 22, 2024
953f058
Refactor instrDesc init
amanasifkhalid Jan 22, 2024
b57d6cc
Create insEncodeImm8 helper
amanasifkhalid Jan 23, 2024
5239b91
merge from main
amanasifkhalid Jan 23, 2024
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3 changes: 2 additions & 1 deletion src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2241,7 +2241,8 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size,
{
if (emitter::emitIns_valid_imm_for_mov(imm, size))
{
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE,
INS_SCALABLE_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
}
else
{
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62 changes: 62 additions & 0 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5613,6 +5613,68 @@ void CodeGen::genArm64EmitterUnitTestsSve()
theEmitter->emitIns_R_F(INS_sve_fmov, EA_SCALABLE, REG_V4, -0.125, INS_OPTS_SCALABLE_S); // FMOV <Zd>.<T>, #<const>
theEmitter->emitIns_R_F(INS_sve_fmov, EA_SCALABLE, REG_V5, 31.0, INS_OPTS_SCALABLE_D); // FMOV <Zd>.<T>, #<const>

// IF_SVE_EB_1A
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V0, -128,
INS_OPTS_SCALABLE_B); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V2, 5,
INS_OPTS_SCALABLE_S); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V3, 127,
INS_OPTS_SCALABLE_D); // DUP <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V4, 0,
INS_OPTS_SCALABLE_B); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V5, -128, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V6, 5, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V7, 127, INS_OPTS_SCALABLE_D,
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}

// IF_SVE_EC_1A
theEmitter->emitIns_R_I(INS_sve_add, EA_SCALABLE, REG_V0, 0,
INS_OPTS_SCALABLE_B); // ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_SCALABLE, REG_V2, 1,
INS_OPTS_SCALABLE_S); // SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_sub, EA_SCALABLE, REG_V3, 128,
INS_OPTS_SCALABLE_D); // SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_subr, EA_SCALABLE, REG_V4, 255,
INS_OPTS_SCALABLE_B); // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_SCALABLE, REG_V5, 5, INS_OPTS_SCALABLE_H,
INS_SCALABLE_OPTS_SHIFT); // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_SCALABLE, REG_V6, 255, INS_OPTS_SCALABLE_S,
INS_SCALABLE_OPTS_SHIFT); // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}

// IF_SVE_ED_1A
theEmitter->emitIns_R_I(INS_sve_smax, EA_SCALABLE, REG_V0, -128,
INS_OPTS_SCALABLE_B); // SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_smax, EA_SCALABLE, REG_V1, 127,
INS_OPTS_SCALABLE_H); // SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_smin, EA_SCALABLE, REG_V2, -128,
INS_OPTS_SCALABLE_S); // SMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_smin, EA_SCALABLE, REG_V3, 127,
INS_OPTS_SCALABLE_D); // SMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_umax, EA_SCALABLE, REG_V4, 0,
INS_OPTS_SCALABLE_B); // UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_umax, EA_SCALABLE, REG_V5, 255,
INS_OPTS_SCALABLE_H); // UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_umin, EA_SCALABLE, REG_V6, 0,
INS_OPTS_SCALABLE_S); // UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_umin, EA_SCALABLE, REG_V7, 255,
INS_OPTS_SCALABLE_D); // UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>

// IF_SVE_EE_1A
theEmitter->emitIns_R_I(INS_sve_mul, EA_SCALABLE, REG_V0, -128,
INS_OPTS_SCALABLE_B); // MUL <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_mul, EA_SCALABLE, REG_V1, 0,
INS_OPTS_SCALABLE_H); // MUL <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_mul, EA_SCALABLE, REG_V2, 5,
INS_OPTS_SCALABLE_S); // MUL <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_I(INS_sve_mul, EA_SCALABLE, REG_V3, 127,
INS_OPTS_SCALABLE_D); // MUL <Zdn>.<T>, <Zdn>.<T>, #<imm>

// IF_SVE_IH_3A
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_SCALABLE, REG_V5, REG_P3, REG_R4, 0,
INS_OPTS_SCALABLE_D); // LD1D {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
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10 changes: 10 additions & 0 deletions src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1443,6 +1443,16 @@ class emitter
assert(!idIsSmallDsc());
idAddr()->_idRegBit = val ? 1 : 0;
}
bool idOptionalShift() const
{
assert(!idIsSmallDsc());
return (idAddr()->_idRegBit == 1);
}
void idOptionalShift(bool val)
{
assert(!idIsSmallDsc());
idAddr()->_idRegBit = val ? 1 : 0;
}
insSvePattern idSvePattern() const
{
assert(!idIsSmallDsc());
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