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[Mono] Add amd64 intrinsics for Vector128 Abs #97024

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merged 4 commits into from
Jan 17, 2024
Merged

[Mono] Add amd64 intrinsics for Vector128 Abs #97024

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fdcad01
[Mono] Add amd64 intrinsics for Vector128 Abs
jkurdek Jan 16, 2024
ed3cecf
added i64 pointer support
jkurdek Jan 16, 2024
8bf19c6
applied review suggestions
jkurdek Jan 17, 2024
cbc9054
fixed types in non ssse3 fallback
jkurdek Jan 17, 2024
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5 changes: 5 additions & 0 deletions src/mono/mono/arch/amd64/amd64-codegen.h
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Expand Up @@ -1194,6 +1194,11 @@ typedef union {
#define amd64_sse_phaddw_reg_reg(inst, dreg, sreg) emit_sse_reg_reg_op4((inst), (dreg), (sreg), 0x66, 0x0f, 0x38, 0x01)
#define amd64_sse_phaddd_reg_reg(inst, dreg, sreg) emit_sse_reg_reg_op4((inst), (dreg), (sreg), 0x66, 0x0f, 0x38, 0x02)
#define amd64_sse_blendpd_reg_reg(inst,dreg,sreg,imm) emit_sse_reg_reg_op4_imm((inst), (dreg), (sreg), 0x66, 0x0f, 0x3a, 0x0d, (imm))

#define amd64_ssse3_pabsb_reg_reg(inst, dreg, reg) emit_sse_reg_reg_op4((inst), (dreg), (reg), 0x66, 0x0f, 0x38, 0x1c)
#define amd64_ssse3_pabsw_reg_reg(inst, dreg, reg) emit_sse_reg_reg_op4((inst), (dreg), (reg), 0x66, 0x0f, 0x38, 0x1d)
#define amd64_ssse3_pabsd_reg_reg(inst, dreg, reg) emit_sse_reg_reg_op4((inst), (dreg), (reg), 0x66, 0x0f, 0x38, 0x1e)

#define amd64_movq_reg_reg(inst,dreg,sreg) emit_sse_reg_reg ((inst), (dreg), (sreg), 0xf3, 0x0f, 0x7e)

/* Generated from x86-codegen.h */
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1 change: 1 addition & 0 deletions src/mono/mono/mini/cpu-amd64.mdesc
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Expand Up @@ -843,6 +843,7 @@ ssse3_shuffle: dest:x src1:x src2:x len:6 clob:1
sse41_dpps_imm: dest:x src1:x src2:x len:7 clob:1
sse41_dppd_imm: dest:x src1:x src2:x len:7 clob:1
vector_andnot: dest:x src1:x src2:x len:7 clob:1
vector_integer_abs: dest:x src1:x len:6

roundp: dest:x src1:x len:10

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19 changes: 19 additions & 0 deletions src/mono/mono/mini/mini-amd64.c
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Expand Up @@ -7607,6 +7607,25 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
case OP_SSSE3_SHUFFLE:
amd64_sse_pshufb_reg_reg (code, ins->dreg, ins->sreg2);
break;
case OP_VECTOR_IABS:
switch (ins->inst_c1) {
case MONO_TYPE_I1:
amd64_ssse3_pabsb_reg_reg(code, ins->dreg, ins->sreg1);
break;
case MONO_TYPE_I2:
amd64_ssse3_pabsw_reg_reg(code, ins->dreg, ins->sreg1);
break;
case MONO_TYPE_I4:
#if TARGET_SIZEOF_VOID_P == 4
case MONO_TYPE_I:
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#endif
amd64_ssse3_pabsd_reg_reg(code, ins->dreg, ins->sreg1);
break;
default:
g_assert_not_reached ();
break;
}
break;
case OP_SSE41_ROUNDP: {
if (ins->inst_c1 == MONO_TYPE_R8)
amd64_sse_roundpd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
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21 changes: 17 additions & 4 deletions src/mono/mono/mini/simd-intrinsics.c
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Expand Up @@ -1475,10 +1475,23 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
ins->inst_c1 = arg0_type;
return ins;
} else {
if (!COMPILE_LLVM (cfg))
// FIXME:
return NULL;
return emit_simd_ins_for_sig (cfg, klass, OP_VECTOR_IABS, -1, arg0_type, fsig, args);
if (COMPILE_LLVM (cfg))
return emit_simd_ins_for_sig (cfg, klass, OP_VECTOR_IABS, -1, arg0_type, fsig, args);

// SSSE3 does not support i64
if (is_SIMD_feature_supported (cfg, MONO_CPU_X86_SSSE3) &&
!(arg0_type == MONO_TYPE_I8 || (TARGET_SIZEOF_VOID_P == 8 && arg0_type == MONO_TYPE_I)))
return emit_simd_ins_for_sig (cfg, klass, OP_VECTOR_IABS, -1, arg0_type, fsig, args);

MonoInst *zero = emit_xzero (cfg, klass);
MonoInst *neg = emit_simd_ins (cfg, klass, OP_XBINOP, zero->dreg, args [0]->dreg);
neg->inst_c0 = OP_ISUB;
neg->inst_c1 = arg0_type;

MonoInst *ins = emit_simd_ins (cfg, klass, OP_XBINOP, args [0]->dreg, neg->dreg);
ins->inst_c0 = OP_IMAX;
ins->inst_c1 = arg0_type;
return ins;
}
#elif defined(TARGET_WASM)
if (type_enum_is_float(arg0_type)) {
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