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Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337

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merged 5 commits into from
Nov 29, 2023
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Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337

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6b951d7
Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A
a74nh Nov 27, 2023
1ee4d4e
INS_OPTS_SCALABLE_n_TO_SIMD_SCALAR
a74nh Nov 28, 2023
47132ec
placeholder
a74nh Nov 28, 2023
71084b3
Block out unsupported instructions
a74nh Nov 29, 2023
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nits
a74nh Nov 29, 2023
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127 changes: 117 additions & 10 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5437,6 +5437,7 @@ void CodeGen::genProfilingLeaveCallback(unsigned helper)
// #define ALL_ARM64_EMITTER_UNIT_TESTS_GENERAL
// #define ALL_ARM64_EMITTER_UNIT_TESTS_ADVSIMD
// #define ALL_ARM64_EMITTER_UNIT_TESTS_SVE
// #define ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
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not sure if it is worth adding a comment in next PR why they are not supported. "The encodings of the instructions cannot be verified currently, so are added under this flag"


#if defined(DEBUG)
void CodeGen::genArm64EmitterUnitTests()
Expand Down Expand Up @@ -10194,11 +10195,11 @@ void CodeGen::genArm64EmitterUnitTests()

// IF_SVE_CN_3A
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15,
INS_OPTS_SCALABLE_H_TO_SIMD); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16,
INS_OPTS_SCALABLE_S_TO_SIMD); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17,
INS_OPTS_SCALABLE_D_TO_SIMD); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */

// IF_SVE_CO_3A
// Note: EA_4BYTE used for B and H (destination register is W)
Expand Down Expand Up @@ -10299,21 +10300,23 @@ void CodeGen::genArm64EmitterUnitTests()

// IF_SVE_HJ_3A
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14,
INS_OPTS_SCALABLE_H_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13,
INS_OPTS_SCALABLE_S_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12,
INS_OPTS_SCALABLE_D_TO_SIMD); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */

// IF_SVE_HL_3A
theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11,
INS_OPTS_SCALABLE_H); /* FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_SCALABLE, REG_V25, REG_P2, REG_V10,
INS_OPTS_SCALABLE_S); /* FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
// These are not yet supported by capstone.
// theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D);
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D);
/* FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
// theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H);
/* FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H);
/* FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_SCALABLE, REG_V28, REG_P0, REG_V7,
INS_OPTS_SCALABLE_S); /* FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_SCALABLE, REG_V29, REG_P1, REG_V6,
Expand All @@ -10337,6 +10340,110 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_sve_fsubr, EA_SCALABLE, REG_V6, REG_P4, REG_V29,
INS_OPTS_SCALABLE_D); /* FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */

// IF_SVE_AF_3A
theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* ANDV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* EORV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */

// IF_SVE_AG_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_1BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
/* ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_2BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
/* EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_4BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_AI_3A
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* UADDV <Dd>, <Pg>, <Zn>.<T> */

// IF_SVE_AJ_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_V7, REG_P22, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
/* ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_AK_3A
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* SMAXV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* SMINV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* UMAXV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* UMINV <V><d>, <Pg>, <Zn>.<T> */

// IF_SVE_AL_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_1BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
/* SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_2BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
/* SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_4BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
/* UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
/* UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_AP_3A
theEmitter->emitIns_R_R_R(INS_sve_cls, EA_SCALABLE, REG_V31, REG_P0, REG_V0,
INS_OPTS_SCALABLE_B); /* CLS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clz, EA_SCALABLE, REG_V30, REG_P1, REG_V1,
INS_OPTS_SCALABLE_H); /* CLZ <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_cnot, EA_SCALABLE, REG_V29, REG_P2, REG_V2,
INS_OPTS_SCALABLE_S); /* CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_cnt, EA_SCALABLE, REG_V28, REG_P3, REG_V3,
INS_OPTS_SCALABLE_D); /* CNT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fabs, EA_SCALABLE, REG_V27, REG_P4, REG_V4,
INS_OPTS_SCALABLE_H); /* FABS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fneg, EA_SCALABLE, REG_V26, REG_P5, REG_V5,
INS_OPTS_SCALABLE_S); /* FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_not, EA_SCALABLE, REG_V25, REG_P6, REG_V6,
INS_OPTS_SCALABLE_B); /* NOT <Zd>.<T>, <Pg>/M, <Zn>.<T> */

// IF_SVE_AQ_3A
theEmitter->emitIns_R_R_R(INS_sve_abs, EA_SCALABLE, REG_V24, REG_P7, REG_V7,
INS_OPTS_SCALABLE_B); /* ABS <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_neg, EA_SCALABLE, REG_V23, REG_P0, REG_V8,
INS_OPTS_SCALABLE_S); /* NEG <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
INS_OPTS_SCALABLE_H); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
INS_OPTS_SCALABLE_S); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_SCALABLE, REG_V22, REG_P1, REG_V9,
INS_OPTS_SCALABLE_D); /* SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxth, EA_SCALABLE, REG_V21, REG_P2, REG_V10,
INS_OPTS_SCALABLE_S); /* SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxth, EA_SCALABLE, REG_V21, REG_P2, REG_V10,
INS_OPTS_SCALABLE_D); /* SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sxtw, EA_SCALABLE, REG_V20, REG_P3, REG_V11,
INS_OPTS_SCALABLE_D); /* SXTW <Zd>.D, <Pg>/M, <Zn>.D */
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
INS_OPTS_SCALABLE_H); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
INS_OPTS_SCALABLE_S); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_SCALABLE, REG_V19, REG_P4, REG_V12,
INS_OPTS_SCALABLE_D); /* UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uxth, EA_SCALABLE, REG_V18, REG_P5, REG_V13,
INS_OPTS_SCALABLE_S); /* UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uxth, EA_SCALABLE, REG_V18, REG_P5, REG_V13,
INS_OPTS_SCALABLE_D); /* UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uxtw, EA_SCALABLE, REG_V17, REG_P6, REG_V14,
INS_OPTS_SCALABLE_D); /* UXTW <Zd>.D, <Pg>/M, <Zn>.D */

#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
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