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Handle Vector multiplication for long/ulong as intrinsic on pre-AVX512 hardware #87142

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Handle Vector multiplication for long/ulong as intrinsic on pre-AVX512 hardware #87142

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7de67f4
Handle Create/CreateBroadcast/CreateScalar/CreateScalarUnsafe for lon…
tannergooding Jun 5, 2023
41d193a
Handle Vector multiplication for long/ulong as intrinsic on pre-AVX51…
tannergooding Jun 5, 2023
0f0444c
Ensure that handling of decomposed long in HWIntrinsicCreate is corre…
tannergooding Jun 6, 2023
9dffc91
Follow the "textbook" algorithm for BigMul
tannergooding Jun 6, 2023
282c03d
Merge remote-tracking branch 'dotnet/main' into fix-87107
tannergooding Aug 7, 2023
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119 changes: 82 additions & 37 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20059,17 +20059,81 @@ GenTree* Compiler::gtNewSimdBinOpNode(
case TYP_ULONG:
{
assert((simdSize == 16) || (simdSize == 32) || (simdSize == 64));
assert(compIsaSupportedDebugOnly(InstructionSet_AVX512DQ_VL));

if (simdSize != 64)
if (compOpportunisticallyDependsOn(InstructionSet_AVX512DQ_VL))
{
intrinsic = NI_AVX512DQ_VL_MultiplyLow;
if (simdSize != 64)
{
intrinsic = NI_AVX512DQ_VL_MultiplyLow;
}
else
{
intrinsic = NI_AVX512DQ_MultiplyLow;
}
}
else
{
intrinsic = NI_AVX512DQ_MultiplyLow;
}
// This follows the "textbook" algorith for big multiplication and matches
// what we do for Math.BigMul, as an example. We don't, however, mask where
// unnecessary. For example, we do not explicitly mask the upper bits for
// op1Lo or op2Lo because they are used in Sse2.Multiply which ignores the
// upper 32-bits of each input. We do, however, need to mask the upper bits
// for mullLo since that's used in `Sse2.Or` which does preserve such bits
// and for tLo since that's used as part of `Sse2.Add`

// ulong op1Lo = (uint)(op1)
// ulong op1Hi = (uint)(op1 >> 32)
GenTree* op1Lo = fgMakeMultiUse(&op1);
GenTree* op1Hi =
gtNewSimdBinOpNode(GT_RSZ, type, op1, gtNewIconNode(32), simdBaseJitType, simdSize);

// ulong op2Lo = (uint)(op2)
// ulong op2Hi = (uint)(op2 >> 32)
GenTree* op2Lo = fgMakeMultiUse(&op2);
GenTree* op2Hi =
gtNewSimdBinOpNode(GT_RSZ, type, op2, gtNewIconNode(32), simdBaseJitType, simdSize);

// ulong mull = op1Lo * op2Lo
GenTree* mull = gtNewSimdHWIntrinsicNode(type, fgMakeMultiUse(&op1Lo), fgMakeMultiUse(&op2Lo),
NI_SSE2_Multiply, CORINFO_TYPE_ULONG, simdSize);

// ulong mask = 0x00000000_FFFFFFFF
simd_t simdVal = {};

for (unsigned i = 0; i < simdSize; i += 8)
{
simdVal.u32[i / 8] = 0xFFFFFFFF;
}

GenTree* mask = gtNewVconNode(type);
memcpy(&mask->AsVecCon()->gtSimdVal, &simdVal, simdSize);

// ulong mullLo = (uint)(mull)
// ulong mullHi = (uint)(mull >> 32)
GenTree* mullLo = gtNewSimdBinOpNode(GT_AND, type, fgMakeMultiUse(&mull), fgMakeMultiUse(&mask),
simdBaseJitType, simdSize);
GenTree* mullHi =
gtNewSimdBinOpNode(GT_RSZ, type, mull, gtNewIconNode(32), simdBaseJitType, simdSize);

// ulong t = (op1Hi * op2Lo) + mullHi
GenTree* t = gtNewSimdHWIntrinsicNode(type, op1Hi, op2Lo, NI_SSE2_Multiply, CORINFO_TYPE_ULONG,
simdSize);
t = gtNewSimdBinOpNode(GT_ADD, type, t, mullHi, CORINFO_TYPE_ULONG, simdSize);

// ulong tLo = (uint)(t)
GenTree* tLo = gtNewSimdBinOpNode(GT_AND, type, t, mask, simdBaseJitType, simdSize);

// ulong tl = (op1Lo * op2Hi) + tLo
GenTree* tl = gtNewSimdHWIntrinsicNode(type, op1Lo, op2Hi, NI_SSE2_Multiply, CORINFO_TYPE_ULONG,
simdSize);
tl = gtNewSimdBinOpNode(GT_ADD, type, tl, tLo, CORINFO_TYPE_ULONG, simdSize);

// return (tl << 32) | mullLo
GenTree* result =
gtNewSimdBinOpNode(GT_LSH, type, tl, gtNewIconNode(32), simdBaseJitType, simdSize);
result = gtNewSimdBinOpNode(GT_OR, type, result, mullLo, simdBaseJitType, simdSize);
return result;
}
break;
}

Expand Down Expand Up @@ -21712,16 +21776,6 @@ GenTree* Compiler::gtNewSimdCreateBroadcastNode(var_types type,
}

#if defined(TARGET_XARCH)
#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !op1->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
unreached();
}
#endif // TARGET_X86

if (simdSize == 64)
{
hwIntrinsicID = NI_Vector512_Create;
Expand Down Expand Up @@ -21825,16 +21879,6 @@ GenTree* Compiler::gtNewSimdCreateScalarNode(var_types type,
}

#if defined(TARGET_XARCH)
#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !op1->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
unreached();
}
#endif // TARGET_X86

if (simdSize == 32)
{
hwIntrinsicID = NI_Vector256_CreateScalar;
Expand Down Expand Up @@ -21970,16 +22014,6 @@ GenTree* Compiler::gtNewSimdCreateScalarUnsafeNode(var_types type,
}

#if defined(TARGET_XARCH)
#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !op1->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
unreached();
}
#endif // TARGET_X86

if (simdSize == 32)
{
hwIntrinsicID = NI_Vector256_CreateScalarUnsafe;
Expand Down Expand Up @@ -24730,25 +24764,36 @@ GenTree* Compiler::gtNewSimdWithElementNode(
#if defined(TARGET_XARCH)
switch (simdBaseType)
{
// Using software fallback if simdBaseType is not supported by hardware
case TYP_BYTE:
case TYP_UBYTE:
{
assert(compIsaSupportedDebugOnly(InstructionSet_SSE41));
break;
}

case TYP_INT:
case TYP_UINT:
assert(compIsaSupportedDebugOnly(InstructionSet_SSE41));
{
// Emulate these using the TYP_FLOAT handling
assert(compIsaSupportedDebugOnly(InstructionSet_SSE2));
break;
}

case TYP_LONG:
case TYP_ULONG:
{
assert(compIsaSupportedDebugOnly(InstructionSet_SSE41_X64));
break;
}

case TYP_DOUBLE:
case TYP_FLOAT:
case TYP_SHORT:
case TYP_USHORT:
{
assert(compIsaSupportedDebugOnly(InstructionSet_SSE2));
break;
}

default:
unreached();
Expand Down
38 changes: 22 additions & 16 deletions src/coreclr/jit/gentree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6512,31 +6512,37 @@ struct GenTreeVecCon : public GenTree
case TYP_LONG:
case TYP_ULONG:
{
#if defined(TARGET_64BIT)
if (arg->IsCnsIntOrI())
if (arg->IsIntegralConst())
{
simdVal.i64[argIdx] = static_cast<int64_t>(arg->AsIntCon()->gtIconVal);
simdVal.i64[argIdx] = static_cast<int64_t>(arg->AsIntConCommon()->LngValue());
return true;
}
#else
if (arg->OperIsLong() && arg->AsOp()->gtOp1->IsCnsIntOrI() && arg->AsOp()->gtOp2->IsCnsIntOrI())

#if !defined(TARGET_64BIT)
if (arg->OperIsLong())
{
// 32-bit targets will decompose GT_CNS_LNG into two GT_CNS_INT
// We need to reconstruct the 64-bit value in order to handle this

INT64 gtLconVal = arg->AsOp()->gtOp2->AsIntCon()->gtIconVal;
gtLconVal <<= 32;
gtLconVal |= arg->AsOp()->gtOp1->AsIntCon()->gtIconVal;
GenTreeOp* argOp = arg->AsOp();

simdVal.i64[argIdx] = gtLconVal;
return true;
}
#endif // TARGET_64BIT
else
{
// We expect the constant to have been already zeroed
assert(simdVal.i64[argIdx] == 0);
GenTree* argOpLo = argOp->gtGetOp1();
GenTree* argOpHi = argOp->gtGetOp2();

if (argOpLo->IsCnsIntOrI() && argOpHi->IsCnsIntOrI())
{
argIdx *= 2;

simdVal.i32[argIdx + 0] = static_cast<int32_t>(argOpLo->AsIntCon()->gtIconVal);
simdVal.i32[argIdx + 1] = static_cast<int32_t>(argOpHi->AsIntCon()->gtIconVal);

return true;
}
}
#endif // !TARGET_64BIT

// We expect the constant to have been already zeroed
assert(simdVal.i64[argIdx] == 0);
break;
}

Expand Down
76 changes: 16 additions & 60 deletions src/coreclr/jit/hwintrinsicxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1479,16 +1479,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
if (sig->numArgs == 1)
{
#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !impStackTop(0).val->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
}
#endif // TARGET_X86

op1 = impPopStack().val;
retNode = gtNewSimdCreateBroadcastNode(retType, op1, simdBaseJitType, simdSize);
break;
Expand Down Expand Up @@ -1623,16 +1613,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType))
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
}
#endif // TARGET_X86

IntrinsicNodeBuilder nodeBuilder(getAllocator(CMK_ASTNode), sig->numArgs);

// TODO-CQ: We don't handle contiguous args for anything except TYP_FLOAT today
Expand Down Expand Up @@ -1677,17 +1657,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
case NI_Vector512_CreateScalar:
{
assert(sig->numArgs == 1);

#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !impStackTop(0).val->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
}
#endif // TARGET_X86

op1 = impPopStack().val;
retNode = gtNewSimdCreateScalarNode(retType, op1, simdBaseJitType, simdSize);
break;
Expand All @@ -1698,17 +1667,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
case NI_Vector512_CreateScalarUnsafe:
{
assert(sig->numArgs == 1);

#if defined(TARGET_X86)
if (varTypeIsLong(simdBaseType) && !impStackTop(0).val->IsIntegralConst())
{
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
}
#endif // TARGET_X86

op1 = impPopStack().val;
retNode = gtNewSimdCreateScalarUnsafeNode(retType, op1, simdBaseJitType, simdSize);
break;
Expand Down Expand Up @@ -2425,21 +2383,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

if (varTypeIsLong(simdBaseType))
{
if (simdSize != 64 && !compOpportunisticallyDependsOn(InstructionSet_AVX512DQ_VL))
{
// TODO-XARCH-CQ: We should support long/ulong multiplication
break;
}
// else if simdSize == 64 then above assert would check if baseline isa supported

#if defined(TARGET_X86)
// TODO-XARCH-CQ: We need to support 64-bit CreateBroadcast
break;
#endif // TARGET_X86
}

CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
var_types argType = TYP_UNKNOWN;
Expand Down Expand Up @@ -3064,34 +3007,47 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

switch (simdBaseType)
{
// Using software fallback if simdBaseType is not supported by hardware
case TYP_BYTE:
case TYP_UBYTE:
case TYP_INT:
case TYP_UINT:
{
if (!compOpportunisticallyDependsOn(InstructionSet_SSE41))
{
return nullptr;
}
break;
}

case TYP_INT:
case TYP_UINT:
{
// int/uint are "properly" supported by SSE4.1 and
// handled using the TYP_FLOAT logic otherwise
break;
}

case TYP_LONG:
case TYP_ULONG:
{
if (!compOpportunisticallyDependsOn(InstructionSet_SSE41_X64))
{
return nullptr;
}
break;
}

case TYP_DOUBLE:
case TYP_FLOAT:
case TYP_SHORT:
case TYP_USHORT:
{
// short/ushort/float/double is supported by SSE2
break;
}

default:
{
unreached();
}
}

GenTree* valueOp = impPopStack().val;
Expand Down
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