Accelerate System.Half arithmetic and conversions with FP16

src/coreclr/inc/clrconfigvalues.h

@@ -701,6 +701,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Atomics,           W("EnableArm64At
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Crc32,             W("EnableArm64Crc32"),          1, "Allows Arm64 Crc32+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Dczva,             W("EnableArm64Dczva"),          1, "Allows Arm64 Dczva+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Dp,                W("EnableArm64Dp"),             1, "Allows Arm64 Dp+ hardware intrinsics to be disabled")
+RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Fp16,              W("EnableArm64Fp16"),           1, "Allows Arm64 Fp16+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rdm,               W("EnableArm64Rdm"),            1, "Allows Arm64 Rdm+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1,              W("EnableArm64Sha1"),           1, "Allows Arm64 Sha1+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256,            W("EnableArm64Sha256"),         1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled")

src/coreclr/inc/corinfoinstructionset.h

@@ -23,39 +23,41 @@ enum CORINFO_InstructionSet
     InstructionSet_Crc32=4,
     InstructionSet_Dp=5,
     InstructionSet_Rdm=6,
-    InstructionSet_Sha1=7,
-    InstructionSet_Sha256=8,
-    InstructionSet_Atomics=9,
-    InstructionSet_Vector64=10,
-    InstructionSet_Vector128=11,
-    InstructionSet_VectorT=12,
-    InstructionSet_Dczva=13,
-    InstructionSet_Rcpc=14,
-    InstructionSet_VectorT128=15,
-    InstructionSet_Rcpc2=16,
-    InstructionSet_Sve=17,
-    InstructionSet_Sve2=18,
-    InstructionSet_Sha3=19,
-    InstructionSet_Sm4=20,
-    InstructionSet_SveAes=21,
-    InstructionSet_SveSha3=22,
-    InstructionSet_SveSm4=23,
-    InstructionSet_Cssc=24,
-    InstructionSet_ArmBase_Arm64=25,
-    InstructionSet_AdvSimd_Arm64=26,
-    InstructionSet_Aes_Arm64=27,
-    InstructionSet_Crc32_Arm64=28,
-    InstructionSet_Dp_Arm64=29,
-    InstructionSet_Rdm_Arm64=30,
-    InstructionSet_Sha1_Arm64=31,
-    InstructionSet_Sha256_Arm64=32,
-    InstructionSet_Sve_Arm64=33,
-    InstructionSet_Sve2_Arm64=34,
-    InstructionSet_Sha3_Arm64=35,
-    InstructionSet_Sm4_Arm64=36,
-    InstructionSet_SveAes_Arm64=37,
-    InstructionSet_SveSha3_Arm64=38,
-    InstructionSet_SveSm4_Arm64=39,
+    InstructionSet_Fp16=7,
+    InstructionSet_Sha1=8,
+    InstructionSet_Sha256=9,
+    InstructionSet_Atomics=10,
+    InstructionSet_Vector64=11,
+    InstructionSet_Vector128=12,
+    InstructionSet_VectorT=13,
+    InstructionSet_Dczva=14,
+    InstructionSet_Rcpc=15,
+    InstructionSet_VectorT128=16,
+    InstructionSet_Rcpc2=17,
+    InstructionSet_Sve=18,
+    InstructionSet_Sve2=19,
+    InstructionSet_Sha3=20,
+    InstructionSet_Sm4=21,
+    InstructionSet_SveAes=22,
+    InstructionSet_SveSha3=23,
+    InstructionSet_SveSm4=24,
+    InstructionSet_Cssc=25,
+    InstructionSet_ArmBase_Arm64=26,
+    InstructionSet_AdvSimd_Arm64=27,
+    InstructionSet_Aes_Arm64=28,
+    InstructionSet_Crc32_Arm64=29,
+    InstructionSet_Dp_Arm64=30,
+    InstructionSet_Rdm_Arm64=31,
+    InstructionSet_Fp16_Arm64=32,
+    InstructionSet_Sha1_Arm64=33,
+    InstructionSet_Sha256_Arm64=34,
+    InstructionSet_Sve_Arm64=35,
+    InstructionSet_Sve2_Arm64=36,
+    InstructionSet_Sha3_Arm64=37,
+    InstructionSet_Sm4_Arm64=38,
+    InstructionSet_SveAes_Arm64=39,
+    InstructionSet_SveSha3_Arm64=40,
+    InstructionSet_SveSm4_Arm64=41,
 #endif // TARGET_ARM64
 #ifdef TARGET_RISCV64
     InstructionSet_RiscV64Base=1,
@@ -271,6 +273,8 @@ struct CORINFO_InstructionSetFlags
             AddInstructionSet(InstructionSet_Dp_Arm64);
         if (HasInstructionSet(InstructionSet_Rdm))
             AddInstructionSet(InstructionSet_Rdm_Arm64);
+        if (HasInstructionSet(InstructionSet_Fp16))
+            AddInstructionSet(InstructionSet_Fp16_Arm64);
         if (HasInstructionSet(InstructionSet_Sha1))
             AddInstructionSet(InstructionSet_Sha1_Arm64);
         if (HasInstructionSet(InstructionSet_Sha256))
@@ -371,6 +375,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
             resultflags.RemoveInstructionSet(InstructionSet_Rdm);
         if (resultflags.HasInstructionSet(InstructionSet_Rdm_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Rdm))
             resultflags.RemoveInstructionSet(InstructionSet_Rdm_Arm64);
+        if (resultflags.HasInstructionSet(InstructionSet_Fp16) && !resultflags.HasInstructionSet(InstructionSet_Fp16_Arm64))
+            resultflags.RemoveInstructionSet(InstructionSet_Fp16);
+        if (resultflags.HasInstructionSet(InstructionSet_Fp16_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Fp16))
+            resultflags.RemoveInstructionSet(InstructionSet_Fp16_Arm64);
         if (resultflags.HasInstructionSet(InstructionSet_Sha1) && !resultflags.HasInstructionSet(InstructionSet_Sha1_Arm64))
             resultflags.RemoveInstructionSet(InstructionSet_Sha1);
         if (resultflags.HasInstructionSet(InstructionSet_Sha1_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha1))
@@ -417,6 +425,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
             resultflags.RemoveInstructionSet(InstructionSet_Dp);
         if (resultflags.HasInstructionSet(InstructionSet_Rdm) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
             resultflags.RemoveInstructionSet(InstructionSet_Rdm);
+        if (resultflags.HasInstructionSet(InstructionSet_Fp16) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
+            resultflags.RemoveInstructionSet(InstructionSet_Fp16);
         if (resultflags.HasInstructionSet(InstructionSet_Sha1) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
             resultflags.RemoveInstructionSet(InstructionSet_Sha1);
         if (resultflags.HasInstructionSet(InstructionSet_Sha256) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
@@ -697,6 +707,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
             return "Rdm";
         case InstructionSet_Rdm_Arm64 :
             return "Rdm_Arm64";
+        case InstructionSet_Fp16 :
+            return "Fp16";
+        case InstructionSet_Fp16_Arm64 :
+            return "Fp16_Arm64";
         case InstructionSet_Sha1 :
             return "Sha1";
         case InstructionSet_Sha1_Arm64 :
@@ -953,6 +967,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
         case READYTORUN_INSTRUCTION_Crc32: return InstructionSet_Crc32;
         case READYTORUN_INSTRUCTION_Dp: return InstructionSet_Dp;
         case READYTORUN_INSTRUCTION_Rdm: return InstructionSet_Rdm;
+        case READYTORUN_INSTRUCTION_Fp16: return InstructionSet_Fp16;
         case READYTORUN_INSTRUCTION_Sha1: return InstructionSet_Sha1;
         case READYTORUN_INSTRUCTION_Sha256: return InstructionSet_Sha256;
         case READYTORUN_INSTRUCTION_Atomics: return InstructionSet_Atomics;

src/coreclr/inc/jiteeversionguid.h

@@ -37,11 +37,11 @@
 
 #include <minipal/guid.h>
 
-constexpr GUID JITEEVersionIdentifier = { /* 5bb9b1e5-9941-4762-a195-351b6a736588 */
-    0x5bb9b1e5,
-    0x9941,
-    0x4762,
-    {0xa1, 0x95, 0x35, 0x1b, 0x6a, 0x73, 0x65, 0x88}
+constexpr GUID JITEEVersionIdentifier = { /* bbcf517b-9525-46b8-bf11-7507778973e7 */
+    0xbbcf517b,
+    0x9525,
+    0x46b8,
+    {0xbf, 0x11, 0x75, 0x07, 0x77, 0x89, 0x73, 0xe7}
   };
 
 #endif // JIT_EE_VERSIONING_GUID_H

src/coreclr/inc/readytoruninstructionset.h

@@ -102,6 +102,8 @@ enum ReadyToRunInstructionSet
     READYTORUN_INSTRUCTION_PackedSimd=92,
     READYTORUN_INSTRUCTION_Cssc=93,
     READYTORUN_INSTRUCTION_Zicond=94,
+    READYTORUN_INSTRUCTION_Fp16=95,
+
 };
 
 #endif // READYTORUNINSTRUCTIONSET_H

src/coreclr/jit/codegen.h

@@ -631,6 +631,7 @@ class CodeGen final : public CodeGenInterface
 #if defined(TARGET_ARM64)
     void genArm64EmitterUnitTestsGeneral();
     void genArm64EmitterUnitTestsAdvSimd();
+    void genArm64EmitterUnitTestsFp16();
     void genArm64EmitterUnitTestsSve();
     void genArm64EmitterUnitTestsPac();
 #endif

src/coreclr/jit/codegenarm64test.cpp

@@ -9183,4 +9183,66 @@ void CodeGen::genArm64EmitterUnitTestsPac()
     theEmitter->emitIns_R_R(INS_pacia, EA_8BYTE, REG_R27, REG_SP); // PACIA <Xd>, <Xn|SP>
     theEmitter->emitIns_R_R(INS_pacib, EA_8BYTE, REG_R28, REG_SP); // PACIB <Xd>, <Xn|SP>
 }
+
+//-----------------------------------------------------------------------------
+// genArm64EmitterUnitTestsFp16: Emit the scalar half-precision (FEAT_FP16)
+// floating-point instructions used to accelerate `System.Half`, so their
+// encodings and disassembly can be verified.
+//
+void CodeGen::genArm64EmitterUnitTestsFp16()
+{
+    emitter* theEmitter = GetEmitter();
+
+    genDefineTempLabel(genCreateTempLabel());
+
+    // IF_DV_3D: scalar half-precision, two source registers
+    theEmitter->emitIns_R_R_R(INS_fadd, EA_2BYTE, REG_V0, REG_V1, REG_V2);      // FADD   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fsub, EA_2BYTE, REG_V3, REG_V4, REG_V5);      // FSUB   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fmul, EA_2BYTE, REG_V6, REG_V7, REG_V8);      // FMUL   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fdiv, EA_2BYTE, REG_V9, REG_V10, REG_V11);    // FDIV   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fnmul, EA_2BYTE, REG_V12, REG_V13, REG_V14);  // FNMUL  Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fmax, EA_2BYTE, REG_V15, REG_V16, REG_V17);   // FMAX   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fmin, EA_2BYTE, REG_V18, REG_V19, REG_V20);   // FMIN   Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fmaxnm, EA_2BYTE, REG_V21, REG_V22, REG_V23); // FMAXNM Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fminnm, EA_2BYTE, REG_V24, REG_V25, REG_V26); // FMINNM Hd, Hn, Hm
+    theEmitter->emitIns_R_R_R(INS_fabd, EA_2BYTE, REG_V27, REG_V28, REG_V29);   // FABD   Hd, Hn, Hm
+
+    // IF_DV_2G: scalar half-precision, one source register
+    theEmitter->emitIns_R_R(INS_fsqrt, EA_2BYTE, REG_V0, REG_V1);     // FSQRT   Hd, Hn
+    theEmitter->emitIns_R_R(INS_frinta, EA_2BYTE, REG_V2, REG_V3);    // FRINTA  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frinti, EA_2BYTE, REG_V4, REG_V5);    // FRINTI  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frintm, EA_2BYTE, REG_V6, REG_V7);    // FRINTM  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frintn, EA_2BYTE, REG_V8, REG_V9);    // FRINTN  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frintp, EA_2BYTE, REG_V10, REG_V11);  // FRINTP  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frintx, EA_2BYTE, REG_V12, REG_V13);  // FRINTX  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frintz, EA_2BYTE, REG_V14, REG_V15);  // FRINTZ  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frecpe, EA_2BYTE, REG_V16, REG_V17);  // FRECPE  Hd, Hn
+    theEmitter->emitIns_R_R(INS_frsqrte, EA_2BYTE, REG_V18, REG_V19); // FRSQRTE Hd, Hn
+
+    // IF_DV_2K: scalar half-precision compare
+    theEmitter->emitIns_R_R(INS_fcmp, EA_2BYTE, REG_V0, REG_V1);  // FCMP   Hn, Hm
+    theEmitter->emitIns_R_R(INS_fcmpe, EA_2BYTE, REG_V2, REG_V3); // FCMPE  Hn, Hm
+
+    // IF_DV_4A: scalar half-precision fused multiply-add
+    theEmitter->emitIns_R_R_R_R(INS_fmadd, EA_2BYTE, REG_V0, REG_V1, REG_V2, REG_V3);  // FMADD  Hd, Hn, Hm, Ha
+    theEmitter->emitIns_R_R_R_R(INS_fnmadd, EA_2BYTE, REG_V4, REG_V5, REG_V6, REG_V7); // FNMADD Hd, Hn, Hm, Ha
+
+    // IF_DV_2J: convert between half and single/double
+    theEmitter->emitIns_R_R(INS_fcvt, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_H_TO_S); // FCVT   Sd, Hn
+    theEmitter->emitIns_R_R(INS_fcvt, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_H_TO_D); // FCVT   Dd, Hn
+    theEmitter->emitIns_R_R(INS_fcvt, EA_2BYTE, REG_V4, REG_V5, INS_OPTS_S_TO_H); // FCVT   Hd, Sn
+    theEmitter->emitIns_R_R(INS_fcvt, EA_2BYTE, REG_V6, REG_V7, INS_OPTS_D_TO_H); // FCVT   Hd, Dn
+
+    // IF_DV_2H: convert half to integer (truncating toward zero)
+    theEmitter->emitIns_R_R(INS_fcvtzs, EA_4BYTE, REG_R0, REG_V1, INS_OPTS_H_TO_4BYTE); // FCVTZS Wd, Hn
+    theEmitter->emitIns_R_R(INS_fcvtzs, EA_8BYTE, REG_R2, REG_V3, INS_OPTS_H_TO_8BYTE); // FCVTZS Xd, Hn
+    theEmitter->emitIns_R_R(INS_fcvtzu, EA_4BYTE, REG_R4, REG_V5, INS_OPTS_H_TO_4BYTE); // FCVTZU Wd, Hn
+    theEmitter->emitIns_R_R(INS_fcvtzu, EA_8BYTE, REG_R6, REG_V7, INS_OPTS_H_TO_8BYTE); // FCVTZU Xd, Hn
+
+    // IF_DV_2I: convert integer to half
+    theEmitter->emitIns_R_R(INS_scvtf, EA_2BYTE, REG_V0, REG_R1, INS_OPTS_4BYTE_TO_H); // SCVTF  Hd, Wn
+    theEmitter->emitIns_R_R(INS_scvtf, EA_2BYTE, REG_V2, REG_R3, INS_OPTS_8BYTE_TO_H); // SCVTF  Hd, Xn
+    theEmitter->emitIns_R_R(INS_ucvtf, EA_2BYTE, REG_V4, REG_R5, INS_OPTS_4BYTE_TO_H); // UCVTF  Hd, Wn
+    theEmitter->emitIns_R_R(INS_ucvtf, EA_2BYTE, REG_V6, REG_R7, INS_OPTS_8BYTE_TO_H); // UCVTF  Hd, Xn
+}
 #endif // defined(TARGET_ARM64) && defined(DEBUG)

src/coreclr/jit/codegenlinear.cpp

@@ -2788,6 +2788,10 @@ void CodeGen::genEmitterUnitTests()
     {
         genArm64EmitterUnitTestsAdvSimd();
     }
+    if (unitTestSectionAll || (strstr(unitTestSection, "fp16") != nullptr))
+    {
+        genArm64EmitterUnitTestsFp16();
+    }
     if (unitTestSectionAll || (strstr(unitTestSection, "sve") != nullptr))
     {
         genArm64EmitterUnitTestsSve();

src/coreclr/jit/compiler.cpp

@@ -6033,6 +6033,11 @@ int Compiler::compCompileAfterInit(CORINFO_MODULE_HANDLE classPtr,
             instructionSetFlags.AddInstructionSet(InstructionSet_Rdm);
         }
 
+        if (JitConfig.EnableArm64Fp16() != 0)
+        {
+            instructionSetFlags.AddInstructionSet(InstructionSet_Fp16);
+        }
+
         if (JitConfig.EnableArm64Sha1() != 0)
         {
             instructionSetFlags.AddInstructionSet(InstructionSet_Sha1);

src/coreclr/jit/compiler.h

@@ -5342,6 +5342,13 @@ class Compiler
 
     NamedIntrinsic lookupPrimitiveFloatNamedIntrinsic(CORINFO_METHOD_HANDLE method, const char* methodName);
     NamedIntrinsic lookupPrimitiveIntNamedIntrinsic(CORINFO_METHOD_HANDLE method, const char* methodName);
+    NamedIntrinsic lookupHalfNamedIntrinsic(CORINFO_METHOD_HANDLE method, const char* methodName);
+#if defined(FEATURE_HW_INTRINSICS) && (defined(TARGET_XARCH) || defined(TARGET_ARM64))
+    NamedIntrinsic lookupHalfIntrinsic(NamedIntrinsic ni);
+#endif // FEATURE_HW_INTRINSICS && (TARGET_XARCH || TARGET_ARM64)
+#if defined(FEATURE_HW_INTRINSICS) && defined(TARGET_XARCH)
+    int lookupHalfRoundingMode(NamedIntrinsic ni);
+#endif // FEATURE_HW_INTRINSICS && TARGET_XARCH
     GenTree* impUnsupportedNamedIntrinsic(unsigned              helper,
                                           CORINFO_METHOD_HANDLE method,
                                           CORINFO_SIG_INFO*     sig,

src/coreclr/jit/emit.h

@@ -2069,18 +2069,20 @@ class emitter
 
 #define PERFSCORE_THROUGHPUT_ZERO 0.0f // Only used for pseudo-instructions that don't generate code
 
-#define PERFSCORE_THROUGHPUT_9X (1.0f / 9.0f)
-#define PERFSCORE_THROUGHPUT_6X (1.0f / 6.0f) // Hextuple issue
-#define PERFSCORE_THROUGHPUT_5X 0.20f         // Pentuple issue
-#define PERFSCORE_THROUGHPUT_4X 0.25f         // Quad issue
-#define PERFSCORE_THROUGHPUT_3X (1.0f / 3.0f) // Three issue
-#define PERFSCORE_THROUGHPUT_2X 0.5f          // Dual issue
+#define PERFSCORE_THROUGHPUT_9X   (1.0f / 9.0f)
+#define PERFSCORE_THROUGHPUT_6X   (1.0f / 6.0f) // Hextuple issue
+#define PERFSCORE_THROUGHPUT_5X   0.20f         // Pentuple issue
+#define PERFSCORE_THROUGHPUT_4X   0.25f         // Quad issue
+#define PERFSCORE_THROUGHPUT_3X   (1.0f / 3.0f) // Three issue
+#define PERFSCORE_THROUGHPUT_2X   0.5f          // Dual issue
+#define PERFSCORE_THROUGHPUT_1P5X (2.0f / 3.0f) // 1.5x issue
 
 #define PERFSCORE_THROUGHPUT_1C 1.0f // Single Issue
 
 #define PERFSCORE_THROUGHPUT_2C   2.0f   // slower - 2 cycles
 #define PERFSCORE_THROUGHPUT_3C   3.0f   // slower - 3 cycles
 #define PERFSCORE_THROUGHPUT_4C   4.0f   // slower - 4 cycles
+#define PERFSCORE_THROUGHPUT_4P5C 4.5f   // slower - 4.5 cycles
 #define PERFSCORE_THROUGHPUT_5C   5.0f   // slower - 5 cycles
 #define PERFSCORE_THROUGHPUT_6C   6.0f   // slower - 6 cycles
 #define PERFSCORE_THROUGHPUT_7C   7.0f   // slower - 7 cycles