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Arm64: Fix loads and stores for stack allocated vectors and masks #128037

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Merged
jakobbotsch merged 3 commits into from
May 12, 2026
Merged

Arm64: Fix loads and stores for stack allocated vectors and masks #128037

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3504b81
Arm64: Fix loads and stores for stack allocated vectors and masks
snickolls-arm May 11, 2026
3cffce0
Prevent assertion in emitInsSve_R_R_I
snickolls-arm May 12, 2026
318473f
Merge branch 'main' into fix-ldr-str-codegen
snickolls-arm May 12, 2026
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6 changes: 2 additions & 4 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8312,7 +8312,6 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va
case INS_sve_ldr:
{
assert(isPredicateRegister(reg1) || isVectorRegister(reg1));
assert(FPbased);

isSimple = false;
size = EA_SCALABLE;
Expand All @@ -8321,7 +8320,7 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va

useRegForImm = true;
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, REG_FP, imm);
codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, reg2, imm);
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reg2 = rsvdReg;
imm = 0;
Expand Down Expand Up @@ -8590,15 +8589,14 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va
case INS_sve_str:
{
assert(isVectorRegister(reg1) || isPredicateRegister(reg1));
assert(FPbased);
isSimple = false;
size = EA_SCALABLE;
attr = size;
fmt = isPredicateRegister(reg1) ? IF_SVE_JG_2A : IF_SVE_JH_2A;

useRegForImm = true;
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, REG_FP, imm);
codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, reg2, imm);
reg2 = rsvdReg;
imm = 0;
}
Expand Down
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