Implement various SVE2 Right Shift intrinsics #116914
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Includes: * ShiftRightAndInsert * ShiftRightArithmeticAdd * ShiftRightArithmeticNarrowingSaturateEven * ShiftRightArithmeticNarrowingSaturateOdd * ShiftRightArithmeticNarrowingSaturateUnsignedEven * ShiftRightArithmeticNarrowingSaturateUnsignedOdd * ShiftRightArithmeticRounded * ShiftRightArithmeticRoundedAdd * ShiftRightArithmeticRoundedNarrowingSaturateEven * ShiftRightArithmeticRoundedNarrowingSaturateOdd * ShiftRightArithmeticRoundedNarrowingSaturateUnsignedEven * ShiftRightArithmeticRoundedNarrowingSaturateUnsignedOdd * ShiftRightLogicalAdd * ShiftRightLogicalNarrowingEven * ShiftRightLogicalNarrowingOdd * ShiftRightLogicalRounded * ShiftRightLogicalRoundedAdd * ShiftRightLogicalRoundedNarrowingEven * ShiftRightLogicalRoundedNarrowingOdd * ShiftRightLogicalRoundedNarrowingSaturateOdd * ShiftRightLogicalRoundedNarrowingSaturateEven
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| /// <summary> | ||
| /// svint16_t svqrshrnt[_n_s32](svint16_t even, svint32_t op1, uint64_t imm2) | ||
| /// SQRSHRNT Ztied.H, Zop1.S, #imm2 |
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The destination register is used as a source here because this instruction only writes the odd numbered elements and leaves the even elements unchanged. The ACLE intrinsic has the even parameter which is the initial state of the destination register.
| public static Vector<byte> ShiftRightAndInsert(Vector<byte> left, Vector<byte> right, [ConstantExpected] byte shift) => ShiftRightAndInsert(left, right, shift); | ||
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| /// <summary> | ||
| /// svint16_t svsri[_n_s16](svint16_t op1, svint16_t op2, uint64_t imm3) |
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| HARDWARE_INTRINSIC(Sve2, ShiftRightArithmeticRoundedNarrowingSaturateUnsignedEven, -1, 2, {INS_invalid, INS_sve_sqrshrunb, INS_invalid, INS_sve_sqrshrunb, INS_invalid, INS_sve_sqrshrunb, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand) | ||
| HARDWARE_INTRINSIC(Sve2, ShiftRightArithmeticRoundedNarrowingSaturateUnsignedOdd, -1, 3, {INS_invalid, INS_sve_sqrshrunt, INS_invalid, INS_sve_sqrshrunt, INS_invalid, INS_sve_sqrshrunt, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) | ||
| HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalAdd, -1, 3, {INS_invalid, INS_sve_usra, INS_invalid, INS_sve_usra, INS_invalid, INS_sve_usra, INS_invalid, INS_sve_usra, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics) | ||
| HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalNarrowingEven, -1, 2, {INS_sve_shrnb, INS_sve_shrnb, INS_sve_shrnb, INS_sve_shrnb, INS_sve_shrnb, INS_sve_shrnb, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand) |
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shrnb just operates on unsigned integer value. @a74nh - do you know why we are exposing ShiftRightLogicalNarrowingEven for signed and unsigned? Similar argument goes for other APIs.
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Signed and unsigned versions exist in the ACLE: https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[sve2]&q=svshrnb
I don't think the signedness of the input really matters, just that everything gets shifted right and narrowed.
If we just had one version, I can imagine it creating lots of casting when used with the wrong type. Similar to how were looking at adding additional type for SVE APIs we did last year.
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/ba-g failures unrelated |
3 participants
Includes:
Contributing towards #115479
@a74nh @kunalspathak