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Teach x86 unwinder about POP ECX being optional optimization #115660

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Merged
merged 2 commits into from
May 16, 2025
Merged

Teach x86 unwinder about POP ECX being optional optimization #115660

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Teach x86 unwinder about POP ECX being optional optimization
filipnavara May 16, 2025
686e3a4
s/epilogBase[0]/epilogBase[offset]/
filipnavara May 16, 2025
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7 changes: 5 additions & 2 deletions src/coreclr/vm/gc_unwind_x86.inl
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Original file line number Diff line number Diff line change
Expand Up @@ -2443,7 +2443,7 @@ void UnwindEspFrameEpilog(

// We have already popped off the frame (excluding the callee-saved registers)

if (epilogBase[0] == X86_INSTR_POP_ECX)
if (epilogBase[offset] == X86_INSTR_POP_ECX)
{
// We may use "POP ecx" for doing "ADD ESP, 4",
// or we may not (in the case of JMP epilogs)
Expand Down Expand Up @@ -2560,8 +2560,11 @@ void UnwindEbpDoubleAlignFrameEpilog(
{
// do nothing before popping the callee-saved registers
}
else if (info->rawStkSize == sizeof(void*))
else if (info->rawStkSize == sizeof(void*) && epilogBase[offset] == X86_INSTR_POP_ECX)
{
// We may use "POP ecx" for doing "ADD ESP, 4",
// or we may not (in the case of JMP epilogs)

// "pop ecx" will make ESP point to the callee-saved registers
if (!InstructionAlreadyExecuted(offset, info->epilogOffs))
ESP += sizeof(void*);
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