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kunalspathak
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APX added 8 new GPR registers and that shifted the base of floating point registers. However the shift was not getting accounted for properly while embedding the unwind code.

Also, while I was there, I realized that we didn't add the mapping of new registers for DWARF CFI unwind.

Fixes:

@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 21, 2025
@kunalspathak kunalspathak changed the title Fix the unwind opcode for new registers Fix the unwind opcode for new APX registers Feb 21, 2025
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@amanasifkhalid
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This might also fix #112286

@saucecontrol
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And #112755 😄

@jakobbotsch
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jakobbotsch commented Feb 21, 2025

Any idea why this didn't show up as 0-size diffs in the original PR? We should be diffing unwind codes in SPMI.

Edit: It looks like we don't:

cr2->applyRelocs(&rc, hotCodeBlock_2, hotCodeSize_2, orig_hotCodeBlock_2);
cr2->applyRelocs(&rc, coldCodeBlock_2, coldCodeSize_2, orig_coldCodeBlock_2);
cr2->applyRelocs(&rc, roDataBlock_2, roDataSize_2, orig_roDataBlock_2);
if (!compareCodeSection(mc, cr1, cr2, hotCodeBlock_1, hotCodeSize_1, roDataBlock_1, roDataSize_1,
orig_hotCodeBlock_1, orig_roDataBlock_1, orig_coldCodeBlock_1, coldCodeSize_1,
hotCodeBlock_2, hotCodeSize_2, roDataBlock_2, roDataSize_2, orig_hotCodeBlock_2,
orig_roDataBlock_2, orig_coldCodeBlock_2, coldCodeSize_2))
return false;
if (!compareCodeSection(mc, cr1, cr2, coldCodeBlock_1, coldCodeSize_1, roDataBlock_1, roDataSize_1,
orig_coldCodeBlock_1, orig_roDataBlock_1, orig_hotCodeBlock_1, hotCodeSize_1,
coldCodeBlock_2, coldCodeSize_2, roDataBlock_2, roDataSize_2, orig_coldCodeBlock_2,
orig_roDataBlock_2, orig_hotCodeBlock_2, hotCodeSize_2))
return false;
if (!compareReadOnlyDataBlock(mc, cr1, cr2, roDataBlock_1, roDataSize_1, orig_roDataBlock_1, roDataBlock_2,
roDataSize_2, orig_roDataBlock_2))
return false;
if (!compareEHInfo(mc, cr1, cr2))
return false;
if (!compareGCInfo(mc, cr1, cr2))
return false;
if (!compareVars(mc, cr1, cr2))
return false;
if (!compareBoundaries(mc, cr1, cr2))
return false;
return true;
. I opened #112807 for it.

@kunalspathak
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/azp run runtime-coreclr libraries-jitstress2-jitstressregs, runtime-coreclr r2r-extra

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Azure Pipelines successfully started running 2 pipeline(s).

@kunalspathak
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kunalspathak commented Feb 22, 2025

It seems there are few failures that needs investigation but are unrelated to the change from this PR. I will investigate to make sure and open GH issues, if needed. But this should be ready for review.

r2rextra failures: https://dev.azure.com/dnceng-public/public/_build/results?buildId=959524&view=ms.vss-test-web.build-test-results-tab&runId=25542994&resultId=123196&paneView=debug

@kunalspathak kunalspathak marked this pull request as ready for review February 22, 2025 03:23
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@dotnet/jit-contrib

code->UnwindOp = (genIsValidFloatReg(reg)) ? UWOP_SAVE_XMM128_FAR : UWOP_SAVE_NONVOL_FAR;
}
code->OpInfo = (BYTE)reg;
code->OpInfo = (BYTE)(genIsValidFloatReg(reg) ? reg - XMMBASE : reg);
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Can we add an assert that genIsValidIntReg(reg) for the else case, to help catch any future bugs or expansions in this space?

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We could even assert on the actual range of the computed value, since the unwind codes are well-defined and if they change, we want the assert to hit.

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let me do it as a follow up PR and merge this as is to unblock weekend runs.

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/ba-g osx/arm64 seems to be timeout errors.

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