[RISC-V] Synthesize some floating constants inline

src/coreclr/jit/codegenriscv64.cpp

@@ -1090,29 +1090,39 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
             emitAttr size       = emitActualTypeSize(tree);
             double   constValue = tree->AsDblCon()->DconValue();
 
+            assert(emitter::isFloatReg(targetReg));
+
             // Make sure we use "fmv.w.x reg, zero" only for positive zero (0.0)
             // and not for negative zero (-0.0)
             if (FloatingPointUtils::isPositiveZero(constValue))
             {
                 // A faster/smaller way to generate 0.0
-                // We will just zero out the entire vector register for both float and double
+                // We will just zero out the entire register for both float and double
                 emit->emitIns_R_R(size == EA_4BYTE ? INS_fmv_w_x : INS_fmv_d_x, size, targetReg, REG_R0);
+                break;
             }
-            else
+
+            if (size == EA_4BYTE)
             {
-                // Get a temp integer register to compute long address.
-                // regNumber addrReg = internalRegisters.GetSingle(tree);
+                uint32_t bits = BitOperations::SingleToUInt32Bits(FloatingPointUtils::convertToSingle(constValue));
+                if ((bits << (32 - 12)) == 0) // if 12 lowest bits are zero, synthesize with a single lui instruction
+                {
+                    regNumber temp = internalRegisters.GetSingle(tree);
 
-                // We must load the FP constant from the constant pool
-                // Emit a data section constant for the float or double constant.
-                CORINFO_FIELD_HANDLE hnd = emit->emitFltOrDblConst(constValue, size);
+                    uint32_t hi20 = bits >> 12;
+                    assert(hi20 != 0);
+                    emit->emitIns_R_I(INS_lui, size, temp, hi20);
+                    emit->emitIns_R_R(INS_fmv_w_x, size, targetReg, temp);
+                    break;
+                }
+            }
 
-                // Load the FP constant.
-                assert(emit->isFloatReg(targetReg));
+            // We must load the FP constant from the constant pool
+            // Emit a data section constant for the float or double constant.
+            CORINFO_FIELD_HANDLE hnd = emit->emitFltOrDblConst(constValue, size);
 
-                // Compute the address of the FP constant and load the data.
-                emit->emitIns_R_C(size == EA_4BYTE ? INS_flw : INS_fld, size, targetReg, REG_NA, hnd, 0);
-            }
+            // Compute the address of the FP constant and load the data.
+            emit->emitIns_R_C(size == EA_4BYTE ? INS_flw : INS_fld, size, targetReg, REG_NA, hnd, 0);
         }
         break;
 

src/coreclr/jit/emitriscv64.h

@@ -180,7 +180,8 @@ static bool isValidUimm5(ssize_t value)
 // Returns true if 'value' is a legal signed immediate 20 bit encoding.
 static bool isValidSimm20(ssize_t value)
 {
-    return -(((int)1) << 19) <= value && value < (((int)1) << 19);
+    value >>= 20;
+    return value == 0 || value == -1;
 };
 
 // Returns true if 'value' is a legal unsigned immediate 20 bit encoding.

src/coreclr/jit/lsrariscv64.cpp

@@ -143,10 +143,18 @@ int LinearScan::BuildNode(GenTree* tree)
 
         case GT_CNS_DBL:
         {
-            // There is no instruction for loading float/double imm directly into FPR.
-            // Reserve int to load constant from memory (IF_LARGELDC)
-            buildInternalIntRegisterDefForNode(tree);
-            buildInternalRegisterUses();
+            emitAttr size = emitActualTypeSize(tree);
+
+            double constValue = tree->AsDblCon()->DconValue();
+            if (!FloatingPointUtils::isPositiveZero(constValue) && size == EA_4BYTE)
+            {
+                uint32_t bits = BitOperations::SingleToUInt32Bits(FloatingPointUtils::convertToSingle(constValue));
+                if ((bits << (32 - 12)) == 0) // if 12 lowest bits are zero, synthesize with a single lui instruction
+                {
+                    buildInternalIntRegisterDefForNode(tree);
+                    buildInternalRegisterUses();
+                }
+            }
         }
             FALLTHROUGH;