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Use resumable leaf frames in CET hijack and in GC stress. #104198
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Tagging subscribers to this area: @mangod9 |
/azp run runtime-coreclr gcstress0x3-gcstress0xc |
Azure Pipelines successfully started running 1 pipeline(s). |
src/coreclr/vm/gccover.cpp
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DWORD_PTR retValRegs[1] = { 0 }; | ||
UINT numberOfRegs = 0; |
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DWORD_PTR retValRegs[1] = { 0 }; | |
UINT numberOfRegs = 0; | |
DWORD_PTR retValReg = 0; |
This can simplified since we are only protecting a single value.
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I think with runtime async the need to protect two returns will be back fairly soon, so i did not simplify to strictly one return.
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Thanks!
The stress failures on OSX arm64 look all preexisting. |
// The legacy X86 GC encoder does not encode the state of return registers at | ||
// call sites, so we must add an extra frame to protect returns. | ||
#ifdef TARGET_X86 | ||
DWORD_PTR retValReg = 0; | ||
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if (afterCallProtect[0]) |
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Given that we only need afterCallProtect
for x86 now, we can also delete the whole bunch of arch-specific code above to compute it for non-x86 platforms.
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There is a lot of cleanup possible since we’ve incremented r2r version.
I’d like to do that in a separate follow up change as that could be larger, but mostly mechanical and unlikely to break anything change.
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We would not need disassemble anything other than x86.
Perhaps x64 will merge with RISC and only x86 will be special.
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For non-x86 it will be just iterating over interruptible locations (partial or full interruptible - just different iterators) and stick HLT there.
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Although that may still require disassembling - to ensure that hlt is on instruction edges.
Thanks!! |
Re: #102680 (comment)