[RISC-V] Add pseudoinstructions to disassembler #102260

Bajtazar · 2024-05-15T14:44:34Z

Adds pseudoinstruction printing to the disassembler. Requested in #102074 (comment)

Part of #84834, cc @dotnet/samsung

This reverts commit a011c43.

dotnet-policy-service · 2024-05-15T14:45:08Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

src/coreclr/jit/emitriscv64.cpp

clamp03

LGTM
Did you check coreclr test? Could you show some dump examples?

Bajtazar · 2024-05-16T12:23:18Z

LGTM Did you check coreclr test? Could you show some dump examples?

Tests passes fine

Examples of disassm:

mv instruction

Prior

            slli           a2, a2, 7
            addi           a2, a2, 0
            ld             a2, 0(a2)

New

            slli           a2, a2, 7
            mv             a2, a2
            ld             a2, 0(a2)

bnezand j instructions

Prior

G_M10072_IG07:  ;; offset=0x0064
            sltiu          a0, s1, 65
            slli           a0, a0, 56
            srli           a0, a0, 56
            addiw          t6, a0, 0
            bne            t6, zero, G_M10072_IG11
            jal            zero, 80

New

G_M10072_IG07:  ;; offset=0x0064
            sltiu          a0, s1, 65
            slli           a0, a0, 56
            srli           a0, a0, 56
            addiw          t6, a0, 0
            bnez           t6, G_M10072_IG11
            j              80

nop instruction

Prior

G_M55990_IG31:  ;; offset=0x1578
            addi           zero, zero, 0

New

G_M55990_IG31:  ;; offset=0x1578
            nop

clamp03 · 2024-05-21T00:30:17Z

@tomeksowi @jakobbotsch @jkotas Could you review this PR?

src/coreclr/jit/emitriscv64.cpp

risc-vv · 2024-05-23T16:57:24Z

RISC-V test results for qemu-prio0-checked: 2718 / 2738 (99.27%)

details

GIT: 6869460


=======================
      passed: 2718
      failed: 3
     skipped: 16
      killed: 1
------------------------
  TOTAL libs: 2738
 TOTAL tests: 2738
   REAL time: 36min 26s 575ms
=======================

failed tests

[44.460s] profiler.unittest.releaseondetach.releaseondetach.sh
    [exitcode-134]: SIGABRT Abort. Managed or native assert, or runtime check such as heap corruption, caused call to abort(). Core dumped.
[28.930s] JIT.Directed.debugging.debuginfo.tester.tester.sh
    [exitcode-  -1]: unknown error
[290.630s] readytorun.determinism.crossgen2determinism.crossgen2determinism.sh
    [exitcode-101]: Unknown exit code.

killed tests

[1810.536s] profiler.eventpipe.reverse_startup.reverse_startup.sh

skipped tests

[0.000s] Interop.MonoAPI.MonoMono.InstallEHCallback.InstallEHCallback.sh
[0.000s] Interop.MonoAPI.MonoMono.PInvokeDetach.PInvokeDetach.sh
[0.000s] Interop.MonoAPI.MonoMono.Thunks.Thunks.sh
[0.000s] tracing.eventpipe.eventsourceerror.eventsourceerror.eventsourceerror.sh
[0.000s] JIT.Directed.arglist.vararg_TargetUnix.vararg_TargetUnix.sh
[0.000s] JIT.opt.ValueNumbering.ExposedLocalsNumbering.ExposedLocalsNumbering.sh
[0.000s] JIT.opt.SSA.MemorySsa.MemorySsa.sh
[0.000s] JIT.Regression.JitBlue.Runtime_57606.Runtime_57606.Runtime_57606.sh
[0.000s] Loader.binding.tracing.BinderTracingTest.Basic.BinderTracingTest.Basic.sh
[0.000s] readytorun.GenericCycleDetection.Depth3Test.Depth3Test.sh
[0.000s] readytorun.DynamicMethodGCStress.DynamicMethodGCStress.DynamicMethodGCStress.sh
[0.000s] baseservices.mono.runningmono.runningmono.sh
[0.000s] baseservices.typeequivalence.signatures.nopiatestil.nopiatestil.sh
[0.000s] baseservices.typeequivalence.istypeequivalent.istypeequivalent.istypeequivalent.sh
[0.000s] baseservices.finalization.CriticalFinalizer.CriticalFinalizer.sh
[0.000s] baseservices.exceptions.stackoverflow.stackoverflowtester.stackoverflowtester.sh

risc-vv · 2024-05-23T17:26:02Z

RISC-V test results for starfive-prio0-checked: 2720 / 2738 (99.34%)

details

GIT: 6869460


=======================
      passed: 2720
      failed: 2
     skipped: 16
      killed: 0
------------------------
  TOTAL libs: 2738
 TOTAL tests: 2738
   REAL time: 1h 4min 5s 272ms
=======================

failed tests

[408.370s] readytorun.determinism.crossgen2determinism.crossgen2determinism.sh
    [exitcode-101]: Unknown exit code.
[726.860s] readytorun.coreroot_determinism.coreroot_determinism.coreroot_determinism.sh
    [exitcode-  1]: unknown error

killed tests

skipped tests

[0.000s] readytorun.DynamicMethodGCStress.DynamicMethodGCStress.DynamicMethodGCStress.sh
[0.000s] readytorun.GenericCycleDetection.Depth3Test.Depth3Test.sh
[0.000s] JIT.Regression.JitBlue.Runtime_57606.Runtime_57606.Runtime_57606.sh
[0.000s] JIT.Directed.arglist.vararg_TargetUnix.vararg_TargetUnix.sh
[0.000s] JIT.opt.SSA.MemorySsa.MemorySsa.sh
[0.000s] JIT.opt.ValueNumbering.ExposedLocalsNumbering.ExposedLocalsNumbering.sh
[0.000s] Loader.binding.tracing.BinderTracingTest.Basic.BinderTracingTest.Basic.sh
[0.000s] Interop.MonoAPI.MonoMono.Thunks.Thunks.sh
[0.000s] Interop.MonoAPI.MonoMono.PInvokeDetach.PInvokeDetach.sh
[0.000s] Interop.MonoAPI.MonoMono.InstallEHCallback.InstallEHCallback.sh
[0.000s] tracing.eventpipe.eventsourceerror.eventsourceerror.eventsourceerror.sh
[0.000s] baseservices.finalization.CriticalFinalizer.CriticalFinalizer.sh
[0.000s] baseservices.mono.runningmono.runningmono.sh
[0.000s] baseservices.exceptions.stackoverflow.stackoverflowtester.stackoverflowtester.sh
[0.000s] baseservices.typeequivalence.istypeequivalent.istypeequivalent.istypeequivalent.sh
[0.000s] baseservices.typeequivalence.signatures.nopiatestil.nopiatestil.sh

risc-vv · 2024-05-23T18:15:12Z

RISC-V test results for qemu-prio1-checked: 9396 / 9443 (99.50%)

details

GIT: 6869460


=======================
      passed: 9396
      failed: 4
     skipped: 42
      killed: 1
------------------------
  TOTAL libs: 9443
 TOTAL tests: 9443
   REAL time: 1h 17min 16s 683ms
=======================

failed tests

[48.630s] profiler.unittest.releaseondetach.releaseondetach.sh
    [exitcode-134]: SIGABRT Abort. Managed or native assert, or runtime check such as heap corruption, caused call to abort(). Core dumped.
[38.310s] JIT.Directed.debugging.debuginfo.tester.tester.sh
    [exitcode-  -1]: unknown error
[349.840s] readytorun.determinism.crossgen2determinism.crossgen2determinism.sh
    [exitcode-101]: Unknown exit code.
[706.940s] readytorun.coreroot_determinism.coreroot_determinism.coreroot_determinism.sh
    [exitcode-  1]: unknown error

killed tests

[1800.886s] profiler.eventpipe.reverse_startup.reverse_startup.sh

skipped tests

[0.000s] Interop.MonoAPI.MonoMono.InstallEHCallback.InstallEHCallback.sh
[0.000s] Interop.MonoAPI.MonoMono.PInvokeDetach.PInvokeDetach.sh
[0.000s] Interop.MonoAPI.MonoMono.Thunks.Thunks.sh
[0.000s] tracing.eventpipe.eventsourceerror.eventsourceerror.eventsourceerror.sh
[0.000s] JIT.Directed.arglist.vararg_TargetUnix.vararg_TargetUnix.sh
[0.000s] JIT.Directed.rvastatics.RVAOrderingTest.RVAOrderingTest.sh
[0.000s] JIT.Directed.PREFIX.volatile.1.arglist_Target_64BIT_volatile.arglist_Target_64BIT_volatile.sh
[0.000s] JIT.Directed.PREFIX.unaligned.4.arglist_Target_64BIT_unaligned_4.arglist_Target_64BIT_unaligned_4.sh
[0.000s] JIT.Directed.PREFIX.unaligned.1.arglist_Target_64BIT_unaligned_1.arglist_Target_64BIT_unaligned_1.sh
[0.000s] JIT.Directed.PREFIX.unaligned.2.arglist_Target_64BIT_unaligned_2.arglist_Target_64BIT_unaligned_2.sh
[0.000s] JIT.opt.ValueNumbering.ExposedLocalsNumbering.ExposedLocalsNumbering.sh
[0.000s] JIT.opt.SSA.MemorySsa.MemorySsa.sh
[0.000s] JIT.Methodical.refany.seq_d.seq_d.sh
[0.000s] JIT.Methodical.refany.seq_r.seq_r.sh
[0.000s] JIT.Methodical.Coverage.arglist_pos.arglist_pos.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b37646.b37646.b37646.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b41852.b41852.b41852.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b31746.b31746.b31746.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M11-Beta1.b41391.b41391.b41391.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M09.5-PDC.b16423.b16423.b16423.sh
[0.000s] JIT.Regression.JitBlue.Runtime_57606.Runtime_57606.Runtime_57606.sh
[0.000s] JIT.Regression.CLR-x86-EJIT.V1-M12-Beta2.b26323.b26323.b26323.sh
[0.000s] JIT.jit64.mcc.interop.mcc_i00.mcc_i00.sh
[0.000s] Loader.binding.tracing.BinderTracingTest.Basic.BinderTracingTest.Basic.sh
[0.000s] readytorun.GenericCycleDetection.Depth3Test.Depth3Test.sh
[0.000s] readytorun.DynamicMethodGCStress.DynamicMethodGCStress.DynamicMethodGCStress.sh
[0.000s] GC.LargeMemory.API.gc.reregisterforfinalize.reregisterforfinalize.sh
[0.000s] GC.LargeMemory.API.gc.getgeneration.getgeneration.sh
[0.000s] GC.LargeMemory.API.gc.collect.collect.sh
[0.000s] GC.LargeMemory.Allocation.finalizertest.finalizertest.sh
[0.000s] GC.Regressions.dev10bugs.536168.536168.536168.sh
[0.000s] GC.Regressions.Github.Runtime_76219.Runtime_76219.Runtime_76219.sh
[0.000s] GC.Features.BackgroundGC.foregroundgc.foregroundgc.sh
[0.000s] GC.Features.LOHFragmentation.lohfragmentation.lohfragmentation.sh
[0.000s] GC.Coverage.271010.271010.sh
[0.000s] baseservices.threading.regressions.2164.foreground-shutdown.foreground-shutdown.sh
[0.000s] baseservices.mono.runningmono.runningmono.sh
[0.000s] baseservices.typeequivalence.signatures.nopiatestil.nopiatestil.sh
[0.000s] baseservices.typeequivalence.istypeequivalent.istypeequivalent.istypeequivalent.sh
[0.000s] baseservices.finalization.CriticalFinalizer.CriticalFinalizer.sh
[0.000s] baseservices.exceptions.stackoverflow.stackoverflowtester.stackoverflowtester.sh
[0.000s] baseservices.exceptions.StackTracePreserve.StackTracePreserveTests.StackTracePreserveTests.sh

risc-vv · 2024-05-23T20:18:42Z

RISC-V test results for starfive-prio1-checked: 9399 / 9443 (99.53%)

details

GIT: 6869460


=======================
      passed: 9399
      failed: 2
     skipped: 42
      killed: 0
------------------------
  TOTAL libs: 9443
 TOTAL tests: 9443
   REAL time: 2h 50min 28s 269ms
=======================

failed tests

[416.290s] readytorun.determinism.crossgen2determinism.crossgen2determinism.sh
    [exitcode-101]: Unknown exit code.
[704.320s] readytorun.coreroot_determinism.coreroot_determinism.coreroot_determinism.sh
    [exitcode-  1]: unknown error

killed tests

skipped tests

[0.000s] readytorun.DynamicMethodGCStress.DynamicMethodGCStress.DynamicMethodGCStress.sh
[0.000s] readytorun.GenericCycleDetection.Depth3Test.Depth3Test.sh
[0.000s] GC.Features.LOHFragmentation.lohfragmentation.lohfragmentation.sh
[0.000s] GC.Features.BackgroundGC.foregroundgc.foregroundgc.sh
[0.000s] GC.Coverage.271010.271010.sh
[0.000s] GC.LargeMemory.Allocation.finalizertest.finalizertest.sh
[0.000s] GC.LargeMemory.API.gc.collect.collect.sh
[0.000s] GC.LargeMemory.API.gc.reregisterforfinalize.reregisterforfinalize.sh
[0.000s] GC.LargeMemory.API.gc.getgeneration.getgeneration.sh
[0.000s] GC.Regressions.dev10bugs.536168.536168.536168.sh
[0.000s] GC.Regressions.Github.Runtime_76219.Runtime_76219.Runtime_76219.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M11-Beta1.b41391.b41391.b41391.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b37646.b37646.b37646.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b31746.b31746.b31746.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M12-Beta2.b41852.b41852.b41852.sh
[0.000s] JIT.Regression.CLR-x86-JIT.V1-M09.5-PDC.b16423.b16423.b16423.sh
[0.000s] JIT.Regression.JitBlue.Runtime_57606.Runtime_57606.Runtime_57606.sh
[0.000s] JIT.Regression.CLR-x86-EJIT.V1-M12-Beta2.b26323.b26323.b26323.sh
[0.000s] JIT.Directed.arglist.vararg_TargetUnix.vararg_TargetUnix.sh
[0.000s] JIT.Directed.rvastatics.RVAOrderingTest.RVAOrderingTest.sh
[0.000s] JIT.Directed.PREFIX.volatile.1.arglist_Target_64BIT_volatile.arglist_Target_64BIT_volatile.sh
[0.000s] JIT.Directed.PREFIX.unaligned.4.arglist_Target_64BIT_unaligned_4.arglist_Target_64BIT_unaligned_4.sh
[0.000s] JIT.Directed.PREFIX.unaligned.2.arglist_Target_64BIT_unaligned_2.arglist_Target_64BIT_unaligned_2.sh
[0.000s] JIT.Directed.PREFIX.unaligned.1.arglist_Target_64BIT_unaligned_1.arglist_Target_64BIT_unaligned_1.sh
[0.000s] JIT.jit64.mcc.interop.mcc_i00.mcc_i00.sh
[0.000s] JIT.opt.SSA.MemorySsa.MemorySsa.sh
[0.000s] JIT.opt.ValueNumbering.ExposedLocalsNumbering.ExposedLocalsNumbering.sh
[0.000s] JIT.Methodical.Coverage.arglist_pos.arglist_pos.sh
[0.000s] JIT.Methodical.refany.seq_d.seq_d.sh
[0.000s] JIT.Methodical.refany.seq_r.seq_r.sh
[0.000s] Loader.binding.tracing.BinderTracingTest.Basic.BinderTracingTest.Basic.sh
[0.000s] Interop.MonoAPI.MonoMono.Thunks.Thunks.sh
[0.000s] Interop.MonoAPI.MonoMono.PInvokeDetach.PInvokeDetach.sh
[0.000s] Interop.MonoAPI.MonoMono.InstallEHCallback.InstallEHCallback.sh
[0.000s] tracing.eventpipe.eventsourceerror.eventsourceerror.eventsourceerror.sh
[0.000s] baseservices.finalization.CriticalFinalizer.CriticalFinalizer.sh
[0.000s] baseservices.mono.runningmono.runningmono.sh
[0.000s] baseservices.threading.regressions.2164.foreground-shutdown.foreground-shutdown.sh
[0.000s] baseservices.exceptions.stackoverflow.stackoverflowtester.stackoverflowtester.sh
[0.000s] baseservices.exceptions.StackTracePreserve.StackTracePreserveTests.StackTracePreserveTests.sh
[0.000s] baseservices.typeequivalence.istypeequivalent.istypeequivalent.istypeequivalent.sh
[0.000s] baseservices.typeequivalence.signatures.nopiatestil.nopiatestil.sh

jakobbotsch

Can you please fix the conflicts?

risc-vv · 2024-05-28T08:11:26Z

RISC-V testing failed on init-build

details

GIT: a4381bd

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Switched to a new branch 'build-net'
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3506 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3506 (offset 3 lines).
Hunk #2 succeeded at 3555 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3508 (offset 3 lines).
Hunk #2 succeeded at 3532 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3508 (offset 3 lines).
Hunk #2 succeeded at 3570 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3347 (offset 3 lines).
Hunk #2 succeeded at 3413 (offset 3 lines).
Hunk #3 succeeded at 3822 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.h...
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3825 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3347 (offset 3 lines).
Hunk #2 succeeded at 3367 (offset 3 lines).
Hunk #3 succeeded at 3457 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3478 (offset 3 lines).
Hunk #2 succeeded at 3516 (offset 3 lines).
Hunk #3 succeeded at 3822 (offset 10 lines).
Hunk #4 succeeded at 3901 (offset 10 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3428 (offset 3 lines).
Hunk #2 succeeded at 3531 (offset 3 lines).
Hunk #3 succeeded at 3908 (offset 10 lines).
Checking patch src/coreclr/jit/codegenriscv64.cpp...
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
{
    code_t code = emitInsCode(ins);

    if (INS_mov == ins)
    {
        assert(isGeneralRegisterOrR0(reg1));
        assert(isGeneralRegisterOrR0(reg2));

error: patch failed: src/coreclr/jit/emitriscv64.cpp:588
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop,           "nop",            0,    0x00000013)

//// R_R
INST(mov,           "mov",            0,    0x00000013)

////R_I
INST(lui,           "lui",            0,    0x00000037)

error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/codegenriscv64.cpp...
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
inline bool emitter::emitInsMayWriteToGCReg(instruction ins)
{
    assert(ins != INS_invalid);
    return (ins <= INS_remuw) && (ins >= INS_mv) && !(ins >= INS_jal && ins <= INS_bgeu && ins != INS_jalr) &&
                   (CodeGenInterface::instInfo[ins] & ST) == 0
               ? true
               : false;

error: patch failed: src/coreclr/jit/emitriscv64.cpp:141
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop,           "nop",            0,    0x00000013)

//// R_R
INST(mv,            "mv",             0,    0x00000013)

////R_I
INST(lui,           "lui",            0,    0x00000037)

error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/instrsriscv64.h...
error: while searching for:
INST(nop,           "nop",            0,    0x00000013)

//// R_R
INST(mov,           "mov",            0,    0x00000013)

////R_I
INST(lui,           "lui",            0,    0x00000037)

error: patch failed: src/coreclr/jit/instrsriscv64.h:35
error: src/coreclr/jit/instrsriscv64.h: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3360 (offset 3 lines).
Hunk #2 succeeded at 3373 (offset 3 lines).
Hunk #3 succeeded at 3524 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3540 (offset 3 lines).
Hunk #2 succeeded at 3562 (offset 3 lines).
Hunk #3 succeeded at 3587 (offset 3 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
                case 0x0: // ADDIW
                    printf("addiw          %s, %s, %d\n", rd, rs1, imm12);
                    return;
                case 0x1:                                                         // SLLIW
                    printf("slliw          %s, %s, %d\n", rd, rs1, imm12 & 0x3f); // 6 BITS for SHAMT in RISCV64
                    return;
                case 0x5: // SRLIW & SRAIW
                    if (((code >> 30) & 0x1) == 0)
                    {
                        printf("srliw          %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64
                    }
                    else
                    {
                        printf("sraiw          %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5BITS for SHAMT in RISCV64
                    }
                    return;
                default:
                    printf("RISCV64 illegal instruction: 0x%08X\n", code);
                    return;
            }
        }
        case 0x33:

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3614
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
                case 0x5: // SRLIW & SRAIW
                {
                    static constexpr unsigned kLogicalShiftFunct7    = 0x00;
                    static constexpr unsigned kArithmeticShiftFunct7 = 0x30;

                    unsigned funct7 = (imm12 >> 5) & 0x7f;
                    if (funct7 == kLogicalShiftFunct7)

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3631
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
                case 0x1: // SLLIW
                {
                    unsigned funct7 = (imm12 >> 5) & 0x7f;
                    // SLLI's instruction code's upper 7 bits have to be equal to zero
                    if (funct7 == 0)
                    {
                        printf("slliw          %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5 BITS for SHAMT in RISCV64

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3617
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3563 (offset 3 lines).
error: while searching for:
                    return;
                case 0x5: // SRLIW & SRAIW
                {
                    static constexpr unsigned kLogicalShiftFunct7    = 0x00;
                    static constexpr unsigned kArithmeticShiftFunct7 = 0x20;

                    unsigned funct7 = (imm12 >> 5) & 0x7f;
                    if (funct7 == kLogicalShiftFunct7)

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3630
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3541 (offset 3 lines).
error: while searching for:
                    return;
                case 0x1: // SLLIW
                {
                    unsigned funct7 = (imm12 >> 5) & 0x7f;
                    // SLLIW's instruction code's upper 7 bits have to be equal to zero
                    if (funct7 == 0)
                    {
                        printf("slliw          %s, %s, %d\n", rd, rs1, imm12 & 0x1f); // 5 BITS for SHAMT in RISCV64
                    }

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3616
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3644 (offset -14 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3733 (offset -14 lines).
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
                    break;
                case 0x1: // SLLI
                {
                    static constexpr kSlliFunct6 = 0b000000;

                    unsigned funct6 = (imm12 >> 6) & 0x3f;
                    // SLLI's instruction code's upper 6 bits have to be equal to zero

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3538
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
error: while searching for:
                    switch (opcode3)
                    {
                        case 0x0: // ADDW
                            return;
                            return;
                        case 0x1: // SLLW
                            printf("sllw           %s, %s, %s\n", rd, rs1, rs2);
                            return;
                        case 0x5: // SRLW
                    {
                            return;
                        default:
                            return emitDispIllegalInstruction(code);

error: patch failed: src/coreclr/jit/emitriscv64.cpp:3759
error: src/coreclr/jit/emitriscv64.cpp: patch does not apply
Checking patch src/coreclr/jit/emitriscv64.cpp...
Hunk #1 succeeded at 3591 (offset 1 line).

Bajtazar · 2024-05-29T11:40:04Z

Can you please fix the conflicts?

Conflicts have been fixed. Could you please review new changes?

* [RISC-V] Reworked emitDispInsName a bit to ease further development * [RISC-V] Little improvements * [RISC-V] Refactored code * [RISC-V] Added mv and nop pseudoinstructions to disasm * [RISC-V] Added branch pseudos to disasm * [RISC-V] Removed dead code * [RISC-V] Fixes * [RISC-V] Added j pseudoinstruction to disasm * [RISC-V] Improved readability * [RISC-V] Fixed mov pseudoinstruction * Revert "[RISC-V] Fixed mov pseudoinstruction" This reverts commit a011c43. * [RISC-V] Fixed mov printing name * [RISC-V] After review changes * [RISC-V] More fixes after review * [RISC-V] Adjusted 32-bit shift disasm to changes * [RISC-V] Fixed bug * [RISC-V] Fixed comment * [RISC-V] Changed constants' literal type * [RISC-V] Added more constants * [RISC-V] Reinforced printing 1 * [RISC-V] Reinforced printing 2 * [RISC-V] Fixed bug * [RISC-V] Resolved more bugs * [RISC-V] Removed dead assert

Bajtazar added 11 commits May 15, 2024 09:58

[RISC-V] Reworked emitDispInsName a bit to ease further development

f501f68

[RISC-V] Little improvements

344771c

[RISC-V] Refactored code

bac35dd

[RISC-V] Added mv and nop pseudoinstructions to disasm

ca5bf3d

[RISC-V] Added branch pseudos to disasm

15d5830

[RISC-V] Removed dead code

f27b4f6

[RISC-V] Fixes

fb27640

[RISC-V] Added j pseudoinstruction to disasm

0cf743e

[RISC-V] Improved readability

a9964cb

[RISC-V] Fixed mov pseudoinstruction

a011c43

Revert "[RISC-V] Fixed mov pseudoinstruction"

ebf66d9

This reverts commit a011c43.

dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 15, 2024

dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label May 15, 2024

build-analysis bot mentioned this pull request May 15, 2024

NativeAOT legs timing out in CI #102239

Closed

clamp03 assigned Bajtazar May 15, 2024

clamp03 added the arch-riscv Related to the RISC-V architecture label May 15, 2024

clamp03 reviewed May 15, 2024

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src/coreclr/jit/emitriscv64.cpp Show resolved Hide resolved

clamp03 reviewed May 15, 2024

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src/coreclr/jit/emitriscv64.cpp Outdated Show resolved Hide resolved

clamp03 approved these changes May 15, 2024

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tomeksowi reviewed May 16, 2024

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src/coreclr/jit/emitriscv64.cpp Outdated Show resolved Hide resolved

Bajtazar added 6 commits May 16, 2024 09:57

[RISC-V] Fixed mov printing name

258b0c6

[RISC-V] After review changes

dcba8e1

[RISC-V] More fixes after review

f100010

[RISC-V] Adjusted 32-bit shift disasm to changes

d69fa7b

[RISC-V] Fixed bug

92c0cd2

[RISC-V] Fixed comment

b7e4f65

tomeksowi approved these changes May 16, 2024

View reviewed changes

src/coreclr/jit/emitriscv64.cpp Outdated Show resolved Hide resolved

Bajtazar added 2 commits May 16, 2024 11:33

[RISC-V] Changed constants' literal type

093193b

[RISC-V] Added more constants

cda08a2

Bajtazar added 4 commits May 16, 2024 12:09

[RISC-V] Reinforced printing 1

e9b73ef

[RISC-V] Reinforced printing 2

5fe1e11

[RISC-V] Fixed bug

71644f3

[RISC-V] Resolved more bugs

a3c4f19

Bajtazar requested review from tomeksowi and clamp03 May 16, 2024 10:47

clamp03 reviewed May 16, 2024

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clamp03 requested review from jkotas and jakobbotsch May 21, 2024 00:29

tomeksowi approved these changes May 21, 2024

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src/coreclr/jit/emitriscv64.cpp Outdated Show resolved Hide resolved

[RISC-V] Removed dead assert

6869460

sirntar approved these changes May 22, 2024

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jakobbotsch approved these changes May 27, 2024

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Merge branch 'main' into riscv-add-pseudo-to-disasm

a4381bd

build-analysis bot mentioned this pull request May 28, 2024

BinderTracingTest.ResolutionFlow.cmd Timed Out #97735

Closed

jakobbotsch merged commit d9bc680 into dotnet:main May 29, 2024
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[RISC-V] Add pseudoinstructions to disassembler #102260

[RISC-V] Add pseudoinstructions to disassembler #102260

Bajtazar commented May 15, 2024

dotnet-policy-service bot commented May 15, 2024

clamp03 left a comment

Bajtazar commented May 16, 2024

clamp03 commented May 21, 2024

risc-vv commented May 23, 2024

risc-vv commented May 23, 2024

risc-vv commented May 23, 2024

risc-vv commented May 23, 2024

jakobbotsch left a comment

risc-vv commented May 28, 2024

Bajtazar commented May 29, 2024

[RISC-V] Add pseudoinstructions to disassembler #102260

[RISC-V] Add pseudoinstructions to disassembler #102260

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Bajtazar commented May 15, 2024

dotnet-policy-service bot commented May 15, 2024

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Bajtazar commented May 16, 2024

clamp03 commented May 21, 2024

risc-vv commented May 23, 2024

RISC-V test results for qemu-prio0-checked: 2718 / 2738 (99.27%)

risc-vv commented May 23, 2024

RISC-V test results for starfive-prio0-checked: 2720 / 2738 (99.34%)

risc-vv commented May 23, 2024

RISC-V test results for qemu-prio1-checked: 9396 / 9443 (99.50%)

risc-vv commented May 23, 2024

RISC-V test results for starfive-prio1-checked: 9399 / 9443 (99.53%)

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risc-vv commented May 28, 2024

RISC-V testing failed on init-build

Bajtazar commented May 29, 2024