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snickolls-armsnickolls-arm
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Make the source encoding for groups IF_SVE_FZ_2A and IF_SVE_HG_2A consistent with other groups with similar operands (#100089)
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4 files changed

+42
-23
lines changed

4 files changed

+42
-23
lines changed

‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6329,16 +6329,16 @@ void CodeGen::genArm64EmitterUnitTestsSve()
63296329
INS_OPTS_SCALABLE_S); // URSQRTE <Zd>.S, <Pg>/M, <Zn>.S
63306330

63316331
// IF_SVE_FZ_2A
6332-
theEmitter->emitIns_R_R(INS_sve_sqcvtn, EA_SCALABLE, REG_V0, REG_V1); // SQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
6333-
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V7); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
6334-
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V15); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
6332+
theEmitter->emitIns_R_R(INS_sve_sqcvtn, EA_SCALABLE, REG_V0, REG_V2); // SQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
6333+
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V8); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
6334+
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V16); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
63356335

63366336
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
63376337
// IF_SVE_HG_2A
6338-
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V1); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
6339-
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V3); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
6340-
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V7); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
6341-
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V15); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
6338+
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V2); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
6339+
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V4); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
6340+
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V8); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
6341+
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V16); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
63426342
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
63436343

63446344
// IF_SVE_GA_2A

‎src/coreclr/jit/emitarm64.cpp‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1787,6 +1787,7 @@ void emitter::emitInsSanityCheck(instrDesc* id)
17871787
assert(id->idInsOpt() == INS_OPTS_SCALABLE_H);
17881788
assert(isVectorRegister(id->idReg1())); // nnnn
17891789
assert(isVectorRegister(id->idReg2())); // ddddd
1790+
assert(isEvenRegister(id->idReg2()));
17901791
assert(isScalableVectorSize(id->idOpSize()));
17911792
break;
17921793

@@ -1828,14 +1829,16 @@ void emitter::emitInsSanityCheck(instrDesc* id)
18281829

18291830
case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
18301831
assert(insOptsNone(id->idInsOpt()));
1831-
assert(isVectorRegister(id->idReg1())); // ddddd
1832-
assert(isLowVectorRegister(id->idReg2())); // nnnn
1832+
assert(isVectorRegister(id->idReg1())); // ddddd
1833+
assert(isVectorRegister(id->idReg2())); // nnnn
1834+
assert(isEvenRegister(id->idReg2()));
18331835
break;
18341836

18351837
case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
18361838
assert(insOptsNone(id->idInsOpt()));
1837-
assert(isVectorRegister(id->idReg1())); // ddddd
1838-
assert(isLowVectorRegister(id->idReg2())); // nnnn
1839+
assert(isVectorRegister(id->idReg1())); // ddddd
1840+
assert(isVectorRegister(id->idReg2())); // nnnn
1841+
assert(isEvenRegister(id->idReg2()));
18391842
break;
18401843

18411844
case IF_SVE_GD_2A: // .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow
@@ -17376,19 +17379,15 @@ void emitter::emitDispInsHelp(
1737617379
case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
1737717380
{
1737817381
emitDispSveReg(id->idReg1(), INS_OPTS_SCALABLE_H, true);
17379-
const unsigned baseRegNum = id->idReg2() - REG_FP_FIRST;
17380-
const regNumber regNum = (regNumber)((baseRegNum * 2) + REG_FP_FIRST);
17381-
emitDispSveConsecutiveRegList(regNum, 2, INS_OPTS_SCALABLE_S, false);
17382+
emitDispSveConsecutiveRegList(id->idReg2(), 2, INS_OPTS_SCALABLE_S, false);
1738217383
break;
1738317384
}
1738417385

1738517386
// <Zd>.B, {<Zn1>.H-<Zn2>.H }
1738617387
case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
1738717388
{
1738817389
emitDispSveReg(id->idReg1(), INS_OPTS_SCALABLE_B, true);
17389-
const unsigned baseRegNum = id->idReg2() - REG_FP_FIRST;
17390-
const regNumber regNum = (regNumber)((baseRegNum * 2) + REG_FP_FIRST);
17391-
emitDispSveConsecutiveRegList(regNum, 2, INS_OPTS_SCALABLE_H, false);
17390+
emitDispSveConsecutiveRegList(id->idReg2(), 2, INS_OPTS_SCALABLE_H, false);
1739217391
break;
1739317392
}
1739417393

‎src/coreclr/jit/emitarm64.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1187,6 +1187,23 @@ inline static bool isHighPredicateRegister(regNumber reg)
11871187
return (reg >= REG_PREDICATE_HIGH_FIRST) && (reg <= REG_PREDICATE_HIGH_LAST);
11881188
}
11891189

1190+
inline static bool isEvenRegister(regNumber reg)
1191+
{
1192+
if (isGeneralRegister(reg))
1193+
{
1194+
return ((reg - REG_INT_FIRST) % 2 == 0);
1195+
}
1196+
else if (isVectorRegister(reg))
1197+
{
1198+
return ((reg - REG_FP_FIRST) % 2) == 0;
1199+
}
1200+
else
1201+
{
1202+
assert(isPredicateRegister(reg));
1203+
return ((reg - REG_PREDICATE_FIRST) % 2) == 0;
1204+
}
1205+
}
1206+
11901207
inline static bool insOptsNone(insOpts opt)
11911208
{
11921209
return (opt == INS_OPTS_NONE);

‎src/coreclr/jit/emitarm64sve.cpp‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2118,8 +2118,9 @@ void emitter::emitInsSve_R_R(instruction ins,
21182118
case INS_sve_uqcvtn:
21192119
case INS_sve_sqcvtun:
21202120
assert(insOptsNone(opt));
2121-
assert(isVectorRegister(reg1)); // ddddd
2122-
assert(isLowVectorRegister(reg2)); // nnnn
2121+
assert(isVectorRegister(reg1)); // ddddd
2122+
assert(isVectorRegister(reg2)); // nnnn
2123+
assert(isEvenRegister(reg2));
21232124
fmt = IF_SVE_FZ_2A;
21242125
break;
21252126

@@ -2129,8 +2130,9 @@ void emitter::emitInsSve_R_R(instruction ins,
21292130
case INS_sve_fcvtnb:
21302131
unreached(); // TODO-SVE: Not yet supported.
21312132
assert(insOptsNone(opt));
2132-
assert(isVectorRegister(reg1)); // ddddd
2133-
assert(isLowVectorRegister(reg2)); // nnnn
2133+
assert(isVectorRegister(reg1)); // ddddd
2134+
assert(isVectorRegister(reg2)); // nnnn
2135+
assert(isEvenRegister(reg2));
21342136
fmt = IF_SVE_HG_2A;
21352137
break;
21362138

@@ -2542,6 +2544,7 @@ void emitter::emitInsSve_R_R_I(instruction ins,
25422544
isRightShift = emitInsIsVectorRightShift(ins);
25432545
assert(isVectorRegister(reg1));
25442546
assert(isVectorRegister(reg2));
2547+
assert(isEvenRegister(reg2));
25452548
assert(opt == INS_OPTS_SCALABLE_H);
25462549
assert(isRightShift); // These are always right-shift.
25472550
assert(isValidVectorShiftAmount(imm, EA_4BYTE, isRightShift));
@@ -10735,8 +10738,8 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)
1073510738
case IF_SVE_FZ_2A: // ................ ......nnnn.ddddd -- SME2 multi-vec extract narrow
1073610739
case IF_SVE_HG_2A: // ................ ......nnnn.ddddd -- SVE2 FP8 downconverts
1073710740
code = emitInsCodeSve(ins, fmt);
10738-
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
10739-
code |= insEncodeReg_V_9_to_6(id->idReg2()); // nnnn
10741+
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
10742+
code |= insEncodeReg_V_9_to_6_Times_Two(id->idReg2()); // nnnn
1074010743
dst += emitOutput_Instr(dst, code);
1074110744
break;
1074210745

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