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github-actions[bot]SwapnilGaikwadamanasifkhalidjeffschwMSFT
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[release/9.0] Add Non-Faulting behaviour for Sve.LoadVector*NonFaulting*() (#106768)
* Add Non-Faulting behaviour for Sve.LoadVector*NonFaulting*() Fixes: #105163 * Fix typo --------- Co-authored-by: Swapnil Gaikwad <[email protected]> Co-authored-by: Aman Khalid <[email protected]> Co-authored-by: Jeff Schwartz <[email protected]>
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‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 78 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -707,10 +707,47 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
707707
{
708708
if (!instrIsRMW)
709709
{
710-
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand
711-
// and `embMaskOp2Reg` is the second operand.
712-
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
713-
embMaskOp2Reg, opt);
710+
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand..
711+
switch (intrinEmbMask.id)
712+
{
713+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
714+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
715+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
716+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
717+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
718+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
719+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
720+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
721+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
722+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
723+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
724+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
725+
case NI_Sve_LoadVectorNonFaulting:
726+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
727+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
728+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
729+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
730+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
731+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
732+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
733+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
734+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
735+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
736+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
737+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
738+
{
739+
740+
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
741+
opt);
742+
break;
743+
}
744+
745+
default:
746+
{
747+
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
748+
embMaskOp2Reg, opt);
749+
}
750+
}
714751
break;
715752
}
716753

@@ -2142,6 +2179,43 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
21422179
break;
21432180
}
21442181

2182+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
2183+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
2184+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
2185+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
2186+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
2187+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
2188+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
2189+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
2190+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
2191+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
2192+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
2193+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
2194+
case NI_Sve_LoadVectorNonFaulting:
2195+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
2196+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
2197+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
2198+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
2199+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
2200+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
2201+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
2202+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
2203+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
2204+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
2205+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
2206+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
2207+
{
2208+
if (intrin.numOperands == 2)
2209+
{
2210+
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR
2211+
// register.
2212+
assert(op2Reg != REG_NA);
2213+
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op2Reg, opt);
2214+
}
2215+
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg);
2216+
break;
2217+
}
2218+
21452219
case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
21462220
case NI_Sve_GatherVectorFirstFaulting:
21472221
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:

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