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SwapnilGaikwadSwapnilGaikwad
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JIT: Add Non-Faulting behaviour for Sve.LoadVector*NonFaulting*() (#106648)
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6 files changed

+266
-82
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6 files changed

+266
-82
lines changed

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 78 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -677,10 +677,47 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
677677
{
678678
if (!instrIsRMW)
679679
{
680-
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand
681-
// and `embMaskOp2Reg` is the second operand.
682-
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
683-
embMaskOp2Reg, opt);
680+
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand..
681+
switch (intrinEmbMask.id)
682+
{
683+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
684+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
685+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
686+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
687+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
688+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
689+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
690+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
691+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
692+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
693+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
694+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
695+
case NI_Sve_LoadVectorNonFaulting:
696+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
697+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
698+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
699+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
700+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
701+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
702+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
703+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
704+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
705+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
706+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
707+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
708+
{
709+
710+
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
711+
opt);
712+
break;
713+
}
714+
715+
default:
716+
{
717+
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
718+
embMaskOp2Reg, opt);
719+
}
720+
}
684721
break;
685722
}
686723

@@ -2089,6 +2126,43 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
20892126
break;
20902127
}
20912128

2129+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
2130+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
2131+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
2132+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
2133+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
2134+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
2135+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
2136+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
2137+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
2138+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
2139+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
2140+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
2141+
case NI_Sve_LoadVectorNonFaulting:
2142+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
2143+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
2144+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
2145+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
2146+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
2147+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
2148+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
2149+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
2150+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
2151+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
2152+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
2153+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
2154+
{
2155+
if (intrin.numOperands == 2)
2156+
{
2157+
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR
2158+
// register.
2159+
assert(op2Reg != REG_NA);
2160+
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op2Reg, opt);
2161+
}
2162+
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg);
2163+
break;
2164+
}
2165+
20922166
case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
20932167
case NI_Sve_GatherVectorFirstFaulting:
20942168
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:

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