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Updating emitInsCanOnlyWriteSSE2OrAVXReg to cover some of the newer instructions. #19141

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Jul 27, 2018
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Updating emitInsCanOnlyWriteSSE2OrAVXReg to cover some of the newer instructions. #19141

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44 changes: 39 additions & 5 deletions src/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1259,15 +1259,43 @@ bool emitter::emitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id)
{
instruction ins = id->idIns();

// The following SSE2 instructions write to a general purpose integer register.
if (!IsSSEOrAVXInstruction(ins) || ins == INS_mov_xmm2i || ins == INS_cvttsd2si || ins == INS_cvttss2si ||
ins == INS_cvtsd2si || ins == INS_cvtss2si || ins == INS_pmovmskb || ins == INS_pextrw || ins == INS_pextrb ||
ins == INS_pextrd || ins == INS_pextrq || ins == INS_extractps)
if (!IsSSEOrAVXInstruction(ins))
{
return false;
}

return true;
switch (ins)
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@tannergooding tannergooding Jul 26, 2018

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New entries are:

case INS_andn:
case INS_blsi:
case INS_blsmsk:
case INS_blsr:
case INS_movmskpd:
case INS_movmskps:
case INS_pdep:
case INS_pext:
case INS_pextrw_sse41:

{
case INS_andn:
case INS_blsi:
case INS_blsmsk:
case INS_blsr:
case INS_cvttsd2si:
case INS_cvttss2si:
case INS_cvtsd2si:
case INS_cvtss2si:
case INS_extractps:
case INS_mov_xmm2i:
case INS_movmskpd:
case INS_movmskps:
case INS_pdep:
case INS_pext:
case INS_pmovmskb:
case INS_pextrb:
case INS_pextrd:
case INS_pextrq:
case INS_pextrw:
case INS_pextrw_sse41:
{
// These SSE instructions write to a general purpose integer register.
return false;
}

default:
{
return true;
}
}
}

/*****************************************************************************
Expand Down Expand Up @@ -10099,6 +10127,8 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
switch (id->idInsFmt())
{
case IF_RWR_ARD:
case IF_RRW_ARD:
case IF_RWR_RRD_ARD:
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@tannergooding tannergooding Jul 26, 2018

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I wasn't actually getting GCStress failures for the RWR_RRD_ARD (as well as the corresponding SRD, MRD, and RRD) entries... However, we are definitely executing SIMD instructions that write integer registers and that use those formats....

Anyone know if there is something I'm missing here?

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@AndyAyersMS AndyAyersMS Jul 26, 2018

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You may just be getting (un)lucky, as the written registers won't always contain GC refs.

emitGCregDeadUpd(id->idReg1(), dst);
break;
default:
Expand Down Expand Up @@ -10522,6 +10552,7 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
{
case IF_RWR_SRD: // Register Write, Stack Read
case IF_RRW_SRD: // Register Read/Write, Stack Read
case IF_RWR_RRD_SRD:
emitGCregDeadUpd(id->idReg1(), dst);
break;
default:
Expand Down Expand Up @@ -10971,6 +11002,8 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
switch (id->idInsFmt())
{
case IF_RWR_MRD:
case IF_RRW_MRD:
case IF_RWR_RRD_MRD:
emitGCregDeadUpd(id->idReg1(), dst);
break;
default:
Expand Down Expand Up @@ -11546,6 +11579,7 @@ BYTE* emitter::emitOutputRR(BYTE* dst, instrDesc* id)

case IF_RWR_RRD:
case IF_RRW_RRD:
case IF_RWR_RRD_RRD:
// INS_movxmm2i writes to reg2.
if (ins == INS_mov_xmm2i)
{
Expand Down